diff options
author | Stephen Boyd | 2018-04-06 13:21:33 -0700 |
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committer | Stephen Boyd | 2018-04-06 13:21:33 -0700 |
commit | 15afa044cba4980aea49fc8e18580a15844f1d5c (patch) | |
tree | fc15a62d25a71262f68636ff6ea532b67e70c385 | |
parent | 401fd20f1f61678d3f71778d32911a941cc70f04 (diff) | |
parent | 5d1c04dde0eb396aec781c825a025e69c48b67cd (diff) | |
parent | 91fab9d26bcbf8614c2389ead327aa704768b639 (diff) | |
parent | 1871f0fcba5debf21d5b0475e6a064dc5c21a026 (diff) |
Merge branches 'clk-ti', 'clk-amlogic', 'clk-tegra' and 'clk-samsung' into clk-next
* clk-ti:
clk: keystone: sci-clk: add support for dynamically probing clocks
clk: ti: add support for clock latching to mux clocks
clk: ti: add support for clock latching to divider clocks
clk: ti: add generic support for clock latching
clk: ti: add support for register read-modify-write low-level operation
dt-bindings: clock: ti: add latching support to mux and divider clocks
* clk-amlogic: (50 commits)
clk: meson: Drop unused local variable and add static
clk: meson: clean-up clk81 clocks
clk: meson: add fdiv clock gates
clk: meson: add mpll pre-divider
clk: meson: axg: add hifi pll clock
clk: meson: axg: add hifi clock bindings
clk: meson: add ROUND_CLOSEST to the pll driver
clk: meson: add gp0 frac parameter for axg and gxl
clk: meson: improve pll driver results with frac
clk: meson: remove special gp0 lock loop
clk: meson: poke pll CNTL last
clk: meson: add fractional part of meson8b fixed_pll
clk: meson: use hhi syscon if available
clk: meson: remove obsolete cpu_clk
clk: meson: rework meson8b cpu clock
clk: meson: split divider and gate part of mpll
clk: meson: migrate plls clocks to clk_regmap
clk: meson: migrate the audio divider clock to clk_regmap
clk: meson: migrate mplls clocks to clk_regmap
clk: meson: add regmap helpers for parm
...
* clk-tegra:
clk: tegra: Fix pll_u rate configuration
clk: tegra: Specify VDE clock rate
clk: tegra20: Correct PLL_C_OUT1 setup
clk: tegra: Mark HCLK, SCLK and EMC as critical
clk: tegra: MBIST work around for Tegra210
clk: tegra: add fence_delay for clock registers
clk: tegra: Add la clock for Tegra210
* clk-samsung: (22 commits)
clk: samsung: Mark a few things static
clk: samsung: Add fout=196608001 Hz EPLL rate entry for exynos4412
clk: samsung: exynos5250: Add missing clocks for FIMC LITE SYSMMU devices
clk: samsung: exynos5420: Add more entries to EPLL rate table
clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk
clk: samsung: exynos5250: Move PD-dependent clocks to Exynos5 sub-CMU
clk: samsung: exynos5420: Move PD-dependent clocks to Exynos5 sub-CMU
clk: samsung: Add Exynos5 sub-CMU clock driver
soc: samsung: pm_domains: Add blacklisting clock handling
clk: samsung: Add compile time PLL rate validators
clk: samsung: s3c2410: Fix PLL rates
clk: samsung: exynos7: Fix PLL rates
clk: samsung: exynos5433: Fix PLL rates
clk: samsung: exynos5260: Fix PLL rates
clk: samsung: exynos5250: Fix PLL rates
clk: samsung: exynos3250: Fix PLL rates
clk: exynos5433: Extend list of available AUD_PLL output frequencies
clk: exynos5433: Add CLK_IGNORE_UNUSED flag to sclk_ioclk_i2s1_bclk
clk: samsung: Add a git tree entry to MAINTAINERS
clk: samsung: Remove redundant dev_err call in exynos_audss_clk_probe()
...