diff options
| author | Palmer Dabbelt | 2018-07-24 17:17:14 -0700 |
|---|---|---|
| committer | Palmer Dabbelt | 2018-10-22 17:37:41 -0700 |
| commit | 1760debb51f73ed3e089c8d4e847554901dee4bb (patch) | |
| tree | 9513702413d63d775e848257dfe76d3a84b6a7b9 | |
| parent | 84df9525b0c27f3ebc2ebb1864fa62a97fdedb7d (diff) | |
RISC-V: Don't set cacheinfo.{physical_line_partition,attributes}
These are just hard coded in the RISC-V port, which doesn't make any
sense. We should probably be setting these from device tree entries
when they exist, but for now I think it's saner to just leave them all
as their default values.
Reviewed-by: Jeremy Linton <jeremy.linton@arm.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| -rw-r--r-- | arch/riscv/kernel/cacheinfo.c | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c index 0bc86e5f8f3f..cb35ffd8ec6b 100644 --- a/arch/riscv/kernel/cacheinfo.c +++ b/arch/riscv/kernel/cacheinfo.c @@ -22,13 +22,6 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, { this_leaf->level = level; this_leaf->type = type; - /* not a sector cache */ - this_leaf->physical_line_partition = 1; - /* TODO: Add to DTS */ - this_leaf->attributes = - CACHE_WRITE_BACK - | CACHE_READ_ALLOCATE - | CACHE_WRITE_ALLOCATE; } static int __init_cache_level(unsigned int cpu) |