diff options
| author | Aurabindo Pillai | 2023-04-04 12:53:54 -0400 |
|---|---|---|
| committer | Alex Deucher | 2023-06-09 12:38:33 -0400 |
| commit | 3cb4807dbf7f47f0a1368f78e7c37b1dd515c2dd (patch) | |
| tree | ca55ed2d98ae21b0227f0b6bd0169f68d25588eb | |
| parent | d6634d4d92eac068e2136afab49dfb15a9efae74 (diff) | |
Revert "drm/amd/display: Only use ODM2:1 policy for high pixel rate displays"
This reverts commit 047783cdd5f604d87398236beb4971abb4d43293 since it
causes higher power consumption for single display use case (4k60).
Also, this patch introduced a 35% performance drop in a Vulkan benchmark.
* The patch disabled the ODM-combination on most popular monitors, including 4K, 2K and FHD monitors at 60Hz.
* ODM-combination can halve the DPP clock to save power, that is the reason why we introduce ODM-combination, and the PM log shows single pipe consumes more power at 4K@60Hz.
* ODM-combination has 2 de-tiled buffer involved, which provides longer self-sustained time, that benefit to the memory power optimization.
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c index 2e6b39fe2613..8d68f02f5147 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c @@ -1918,7 +1918,6 @@ int dcn32_populate_dml_pipes_from_context( context->stream_status[0].plane_count == 1 && !dc_is_hdmi_signal(res_ctx->pipe_ctx[i].stream->signal) && is_h_timing_divisible_by_2(res_ctx->pipe_ctx[i].stream) && - pipe->stream->timing.pix_clk_100hz * 100 > DCN3_2_VMIN_DISPCLK_HZ && dc->debug.enable_single_display_2to1_odm_policy && !vsr_odm_support) { //excluding 2to1 ODM combine on >= 5k vsr pipes[pipe_cnt].pipe.dest.odm_combine_policy = dm_odm_combine_policy_2to1; diff --git a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h index 58826e0aa76e..80bebdf43eca 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h +++ b/drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h @@ -37,7 +37,6 @@ #define DCN3_2_MBLK_WIDTH 128 #define DCN3_2_MBLK_HEIGHT_4BPE 128 #define DCN3_2_MBLK_HEIGHT_8BPE 64 -#define DCN3_2_VMIN_DISPCLK_HZ 717000000 #define DCN3_2_DCFCLK_DS_INIT_KHZ 10000 // Choose 10Mhz for init DCFCLK DS freq #define SUBVP_HIGH_REFRESH_LIST_LEN 3 #define DCN3_2_MAX_SUBVP_PIXEL_RATE_MHZ 1800 |