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authorSatya Priya Kakitapalli2024-01-11 12:02:29 +0530
committerBjorn Andersson2024-01-28 11:54:09 -0600
commit4b3dbd706a6181f19ba63f9265e6f996f01aa76d (patch)
treeaa5f2342d4949144de4da600b742e572121dd4cb
parent2ff787e34174e72a435a79003e5358c962384c3b (diff)
dt-bindings: clock: qcom,gcc-sm8150: Add gcc video resets for sm8150
Add gcc video axic, axi0 and axi1 resets for the global clock controller on sm8150. Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240111-sm8150-dfs-support-v2-2-6edb44c83d3b@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
-rw-r--r--include/dt-bindings/clock/qcom,gcc-sm8150.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/qcom,gcc-sm8150.h b/include/dt-bindings/clock/qcom,gcc-sm8150.h
index dfefd5e8bf6e..921a33f24d33 100644
--- a/include/dt-bindings/clock/qcom,gcc-sm8150.h
+++ b/include/dt-bindings/clock/qcom,gcc-sm8150.h
@@ -239,6 +239,9 @@
#define GCC_USB30_PRIM_BCR 26
#define GCC_USB30_SEC_BCR 27
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 28
+#define GCC_VIDEO_AXIC_CLK_BCR 29
+#define GCC_VIDEO_AXI0_CLK_BCR 30
+#define GCC_VIDEO_AXI1_CLK_BCR 31
/* GCC GDSCRs */
#define PCIE_0_GDSC 0