diff options
| author | Alban Bedel | 2012-11-14 12:58:13 +0100 |
|---|---|---|
| committer | Thierry Reding | 2012-12-06 08:52:07 +0100 |
| commit | a9a18e0691228707230df660dd56364aebf6ea47 (patch) | |
| tree | bb6dceef825dea69d2224f12035dedef45d100a5 | |
| parent | 983290b0625628448ea8907243e3cbceda0a8d74 (diff) | |
pwm: lpc32xx: Fix the PWM polarity
The duty cycles value goes from 1 (99% HIGH) to 256 (0% HIGH) but it
is stored modulo 256 in the register as it is only 8 bits wide.
Signed-off-by: Alban Bedel <alban.bedel@avionic-design.de>
Acked-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Acked-by: Roland Stigge <stigge@antcom.de>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
| -rw-r--r-- | drivers/pwm/pwm-lpc32xx.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/drivers/pwm/pwm-lpc32xx.c b/drivers/pwm/pwm-lpc32xx.c index adb87f0c1633..c9b2eb5932b1 100644 --- a/drivers/pwm/pwm-lpc32xx.c +++ b/drivers/pwm/pwm-lpc32xx.c @@ -49,9 +49,24 @@ static int lpc32xx_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, c = 0; /* 0 set division by 256 */ period_cycles = c; + /* The duty-cycle value is as follows: + * + * DUTY-CYCLE HIGH LEVEL + * 1 99.9% + * 25 90.0% + * 128 50.0% + * 220 10.0% + * 255 0.1% + * 0 0.0% + * + * In other words, the register value is duty-cycle % 256 with + * duty-cycle in the range 1-256. + */ c = 256 * duty_ns; do_div(c, period_ns); - duty_cycles = c; + if (c > 255) + c = 255; + duty_cycles = 256 - c; writel(PWM_ENABLE | PWM_RELOADV(period_cycles) | PWM_DUTY(duty_cycles), lpc32xx->base + (pwm->hwpwm << 2)); |