diff options
| author | Raghavendra Rao Ananta | 2024-07-18 21:55:32 +0000 |
|---|---|---|
| committer | Will Deacon | 2024-07-23 15:29:20 +0100 |
| commit | f3dfcd25455b1cbb3c7e2d19b0a06acc6c7472a5 (patch) | |
| tree | cfe7a4d113da97d5e8e72fa7a2b4f9865ce773fc | |
| parent | 48f6430505c0b0498ee9020ce3cf9558b1caaaeb (diff) | |
arm64/sysreg: Correct the values for GICv4.1
Currently, sysreg has value as 0b0010 for the presence of GICv4.1 in
ID_PFR1_EL1 and ID_AA64PFR0_EL1, instead of 0b0011 as per ARM ARM.
Hence, correct them to reflect ARM ARM.
Signed-off-by: Raghavendra Rao Ananta <rananta@google.com>
Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20240718215532.616447-1-rananta@google.com
Signed-off-by: Will Deacon <will@kernel.org>
| -rw-r--r-- | arch/arm64/tools/sysreg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index a4c1dd4741a4..7ceaa1e0b4bc 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -149,7 +149,7 @@ Res0 63:32 UnsignedEnum 31:28 GIC 0b0000 NI 0b0001 GICv3 - 0b0010 GICv4p1 + 0b0011 GICv4p1 EndEnum UnsignedEnum 27:24 Virt_frac 0b0000 NI @@ -903,7 +903,7 @@ EndEnum UnsignedEnum 27:24 GIC 0b0000 NI 0b0001 IMP - 0b0010 V4P1 + 0b0011 V4P1 EndEnum SignedEnum 23:20 AdvSIMD 0b0000 IMP |