diff options
| author | David Gounaris | 2018-09-03 14:47:29 +0200 |
|---|---|---|
| committer | David S. Miller | 2018-09-03 22:14:41 -0700 |
| commit | 040b7c94e4ec585149f63f429253a493064749c3 (patch) | |
| tree | 12d899dca1a07a795f0f1cf540adfcf49bd15bc5 | |
| parent | 045f77baf6b429a446ace64ba3174783a933398a (diff) | |
net/wan/fsl_ucc_hdlc: GUMR for non tsa mode
The following bits in the GUMR is changed for non
tsa mode: CDS, CTSP and CTSS are set to zero.
When set, there is no tx interrupts from the controller.
Signed-off-by: David Gounaris <david.gounaris@infinera.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/wan/fsl_ucc_hdlc.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c index bb52c4dcf22c..4545c782ef4e 100644 --- a/drivers/net/wan/fsl_ucc_hdlc.c +++ b/drivers/net/wan/fsl_ucc_hdlc.c @@ -97,6 +97,12 @@ static int uhdlc_init(struct ucc_hdlc_private *priv) if (priv->tsa) { uf_info->tsa = 1; uf_info->ctsp = 1; + uf_info->cds = 1; + uf_info->ctss = 1; + } else { + uf_info->cds = 0; + uf_info->ctsp = 0; + uf_info->ctss = 0; } /* This sets HPM register in CMXUCR register which configures a |