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authorBoris Brezillon2014-10-10 15:50:21 +0200
committerNicolas Ferre2014-10-22 10:08:22 +0200
commit106c67af2fb938880edbf43b49dabbd8d2534839 (patch)
tree455a58d847ec8de270ef6397393cb099c1ee08fe
parent7cb4e717d474b118930c3b5fa3a2581eb1fdee72 (diff)
ARM: at91/dt: sam9263: fix PLLB frequencies
PLLB input and output ranges were wrongly copied from at91sam9261 as the datasheet didn't mention explicitly PLLB. Correct their values. This fixes USB. Reported-by: Andreas Henriksson <andreas.henriksson@endian.se> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Tested-by: Andreas Henriksson <andreas.henriksson@endian.se> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
-rw-r--r--arch/arm/boot/dts/at91sam9263.dtsi5
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index d68b3c4862bc..51416c7d0625 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -122,9 +122,10 @@
interrupts-extended = <&pmc AT91_PMC_LOCKB>;
clocks = <&main>;
reg = <1>;
- atmel,clk-input-range = <1000000 5000000>;
+ atmel,clk-input-range = <1000000 32000000>;
#atmel,pll-clk-output-range-cells = <4>;
- atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
+ atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
+ <190000000 240000000 2 1>;
};
mck: masterck {