diff options
| author | Linus Torvalds | 2021-11-03 16:48:32 -0700 |
|---|---|---|
| committer | Linus Torvalds | 2021-11-03 16:48:32 -0700 |
| commit | 2219b0ceefe835b92a8a74a73fe964aa052742a2 (patch) | |
| tree | c2c976be711233fa68de5bb66d5a22a9c169649b | |
| parent | 43e1b12927276cde8052122a24ff796649f09d60 (diff) | |
| parent | fc3d4aeb559f2f704b490f8c1dff82f3b5b142ca (diff) | |
Merge tag 'soc-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC updates from Arnd Bergmann:
"The SoC updates this time are mainly removing obsolete code from the
OMAP2 platform, another step in the eternal cleanup of that platform.
There are two new SoCs getting added: STMicroelectronics stm32mp13 and
Microchip lan966. Both fit into existing platforms and require minimal
changes here.
A couple of MAINTAINER file updates relate to those changes, and
update some file paths"
* tag 'soc-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (28 commits)
MAINTAINERS: Update BCM7XXX entry with additional patterns
MAINTAINERS: add pinctrl-apple-gpio to ARM/APPLE MACHINE
MAINTAINERS: Add pasemi i2c to ARM/APPLE MACHINE
ARM: SPEAr: Update MAINTAINERS entries
ARM: OMAP2+: Drop unused CM defines for am3
ARM: OMAP2+: Drop unused CM and SCRM defines for omap4
ARM: OMAP2+: Drop unused CM and SCRM defines for omap5
ARM: OMAP2+: Drop unused CM defines for dra7
ARM: OMAP2+: Drop unused PRM defines for am3
ARM: OMAP2+: Drop unused PRM defines for am4
ARM: OMAP2+: Drop unused PRM defines for omap4
ARM: OMAP2+: Drop unused PRM defines for omap5
ARM: OMAP2+: Drop unused PRM defines for dra7
ARM: OMAP2+: Fix comment typo
ARM: OMAP2+: Fix typo in some comments
ARM: at91: add basic support for new SoC family lan966
dt-bindings: arm: at91: Document lan966 pcb8291 and pcb8290 boards
ARM: at91: Documentation: add lan966 family
ARM: at91: Documentation: add sama7g5 family
MAINTAINERS: add an entry for NXP S32G boards
...
30 files changed, 135 insertions, 4318 deletions
diff --git a/Documentation/arm/index.rst b/Documentation/arm/index.rst index d4f34ae9e6f4..2bda5461a80b 100644 --- a/Documentation/arm/index.rst +++ b/Documentation/arm/index.rst @@ -55,6 +55,7 @@ SoC-specific documents stm32/stm32h750-overview stm32/stm32f769-overview stm32/stm32f429-overview + stm32/stm32mp13-overview stm32/stm32mp157-overview sunxi diff --git a/Documentation/arm/microchip.rst b/Documentation/arm/microchip.rst index 9c013299fd3b..e721d855f2c9 100644 --- a/Documentation/arm/microchip.rst +++ b/Documentation/arm/microchip.rst @@ -137,6 +137,26 @@ the Microchip website: http://www.microchip.com. http://ww1.microchip.com/downloads/en/DeviceDoc/DS60001476B.pdf + * ARM Cortex-A7 based SoCs + - sama7g5 family + + - sama7g51 + - sama7g52 + - sama7g53 + - sama7g54 (device superset) + + * Datasheet + + Coming soon + + - lan966 family + - lan9662 + - lan9668 + + * Datasheet + + Coming soon + * ARM Cortex-M7 MCUs - sams70 family diff --git a/Documentation/arm/stm32/stm32mp13-overview.rst b/Documentation/arm/stm32/stm32mp13-overview.rst new file mode 100644 index 000000000000..3bb9492dad49 --- /dev/null +++ b/Documentation/arm/stm32/stm32mp13-overview.rst @@ -0,0 +1,37 @@ +=================== +STM32MP13 Overview +=================== + +Introduction +------------ + +The STM32MP131/STM32MP133/STM32MP135 are Cortex-A MPU aimed at various applications. +They feature: + +- One Cortex-A7 application core +- Standard memories interface support +- Standard connectivity, widely inherited from the STM32 MCU family +- Comprehensive security support + +More details: + +- Cortex-A7 core running up to @900MHz +- FMC controller to connect SDRAM, NOR and NAND memories +- QSPI +- SD/MMC/SDIO support +- 2*Ethernet controller +- CAN +- ADC/DAC +- USB EHCI/OHCI controllers +- USB OTG +- I2C, SPI, CAN busses support +- Several general purpose timers +- Serial Audio interface +- LCD controller +- DCMIPP +- SPDIFRX +- DFSDM + +:Authors: + +- Alexandre Torgue <alexandre.torgue@foss.st.com> diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index fba071b9af1d..aad351706117 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -150,6 +150,18 @@ properties: - const: microchip,sama7g5 - const: microchip,sama7 + - description: Microchip LAN9662 PCB8291 Evaluation Board. + items: + - const: microchip,lan9662-pcb8291 + - const: microchip,lan9662 + - const: microchip,lan966 + + - description: Microchip LAN9668 PCB8290 Evaluation Board. + items: + - const: microchip,lan9668-pcb8290 + - const: microchip,lan9668 + - const: microchip,lan966 + - items: - enum: - atmel,sams70j19 diff --git a/MAINTAINERS b/MAINTAINERS index 9ebd990d9edd..0f0b4873b08c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1721,13 +1721,17 @@ B: https://github.com/AsahiLinux/linux/issues C: irc://irc.oftc.net/asahi-dev T: git https://github.com/AsahiLinux/linux.git F: Documentation/devicetree/bindings/arm/apple.yaml +F: Documentation/devicetree/bindings/i2c/apple,i2c.yaml F: Documentation/devicetree/bindings/interrupt-controller/apple,aic.yaml F: Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml F: Documentation/devicetree/bindings/pci/apple,pcie.yaml F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml F: arch/arm64/boot/dts/apple/ +F: drivers/i2c/busses/i2c-pasemi-core.c +F: drivers/i2c/busses/i2c-pasemi-platform.c F: drivers/irqchip/irq-apple-aic.c F: drivers/mailbox/apple-mailbox.c +F: drivers/pinctrl/pinctrl-apple-gpio.c F: include/dt-bindings/interrupt-controller/apple-aic.h F: include/dt-bindings/pinctrl/apple.h F: include/linux/apple-mailbox.h @@ -2315,6 +2319,14 @@ F: arch/arm/boot/dts/nuvoton-wpcm450* F: arch/arm/mach-npcm/wpcm450.c F: drivers/*/*wpcm* +ARM/NXP S32G ARCHITECTURE +M: Chester Lin <clin@suse.com> +R: Andreas Färber <afaerber@suse.de> +R: Matthias Brugger <mbrugger@suse.com> +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: arch/arm64/boot/dts/freescale/s32g*.dts* + ARM/OPENMOKO NEO FREERUNNER (GTA02) MACHINE SUPPORT L: openmoko-kernel@lists.openmoko.org (subscribers-only) S: Orphan @@ -3633,6 +3645,8 @@ F: arch/arm/mm/cache-b15-rac.c F: drivers/bus/brcmstb_gisb.c F: drivers/pci/controller/pcie-brcmstb.c N: brcmstb +N: bcm7038 +N: bcm7120 BROADCOM BDC DRIVER M: Al Cooper <alcooperx@gmail.com> @@ -14987,13 +15001,6 @@ L: linux-omap@vger.kernel.org S: Maintained F: drivers/pinctrl/pinctrl-single.c -PIN CONTROLLER - ST SPEAR -M: Viresh Kumar <vireshk@kernel.org> -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -W: http://www.st.com/spear -F: drivers/pinctrl/spear/ - PKTCDVD DRIVER M: linux-block@vger.kernel.org S: Orphan @@ -17771,21 +17778,17 @@ W: https://github.com/linux-speakup/speakup B: https://github.com/linux-speakup/speakup/issues F: drivers/accessibility/speakup/ -SPEAR CLOCK FRAMEWORK SUPPORT -M: Viresh Kumar <vireshk@kernel.org> -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -W: http://www.st.com/spear -F: drivers/clk/spear/ - -SPEAR PLATFORM SUPPORT +SPEAR PLATFORM/CLOCK/PINCTRL SUPPORT M: Viresh Kumar <vireshk@kernel.org> M: Shiraz Hashim <shiraz.linux.kernel@gmail.com> +M: soc@kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained W: http://www.st.com/spear F: arch/arm/boot/dts/spear* F: arch/arm/mach-spear/ +F: drivers/clk/spear/ +F: drivers/pinctrl/spear/ SPI NOR SUBSYSTEM M: Tudor Ambarus <tudor.ambarus@microchip.com> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig index b09bb2279f7f..02f6b108fd5d 100644 --- a/arch/arm/mach-at91/Kconfig +++ b/arch/arm/mach-at91/Kconfig @@ -67,6 +67,15 @@ config SOC_SAMA7G5 help Select this if you are using one of Microchip's SAMA7G5 family SoC. +config SOC_LAN966 + bool "ARMv7 based Microchip LAN966 SoC family" + depends on ARCH_MULTI_V7 + select DW_APB_TIMER_OF + select ARM_GIC + select MEMORY + help + This enables support for ARMv7 based Microchip LAN966 SoC family. + config SOC_AT91RM9200 bool "AT91RM9200" depends on ARCH_MULTI_V4T diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h index 1e9c23c107b2..553a6267ed57 100644 --- a/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/arch/arm/mach-omap2/cm-regbits-44xx.h @@ -20,71 +20,11 @@ #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H #define OMAP4430_ABE_STATDEP_SHIFT 3 -#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0) -#define OMAP4430_CLKSEL_SHIFT 24 -#define OMAP4430_CLKSEL_WIDTH 0x1 -#define OMAP4430_CLKSEL_MASK (1 << 24) -#define OMAP4430_CLKSEL_0_0_SHIFT 0 -#define OMAP4430_CLKSEL_0_0_WIDTH 0x1 -#define OMAP4430_CLKSEL_0_1_SHIFT 0 -#define OMAP4430_CLKSEL_0_1_WIDTH 0x2 -#define OMAP4430_CLKSEL_24_25_SHIFT 24 -#define OMAP4430_CLKSEL_24_25_WIDTH 0x2 -#define OMAP4430_CLKSEL_60M_SHIFT 24 -#define OMAP4430_CLKSEL_60M_WIDTH 0x1 -#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1 -#define OMAP4430_CLKSEL_CORE_SHIFT 0 -#define OMAP4430_CLKSEL_CORE_WIDTH 0x1 -#define OMAP4430_CLKSEL_DIV_SHIFT 24 -#define OMAP4430_CLKSEL_DIV_WIDTH 0x1 -#define OMAP4430_CLKSEL_FCLK_SHIFT 24 -#define OMAP4430_CLKSEL_FCLK_WIDTH 0x2 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25 -#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1 -#define OMAP4430_CLKSEL_L3_SHIFT 4 -#define OMAP4430_CLKSEL_L3_WIDTH 0x1 -#define OMAP4430_CLKSEL_L4_SHIFT 8 -#define OMAP4430_CLKSEL_L4_WIDTH 0x1 -#define OMAP4430_CLKSEL_OPP_SHIFT 0 -#define OMAP4430_CLKSEL_OPP_WIDTH 0x2 -#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27 -#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3 -#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24) -#define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24) -#define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24) -#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24) -#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24 -#define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1 -#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25 -#define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1 #define OMAP4430_CLKTRCTRL_SHIFT 0 #define OMAP4430_CLKTRCTRL_MASK (0x3 << 0) -#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23 -#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1 -#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0) -#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8 -#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) -#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0 -#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5 -#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0) -#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0) -#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) -#define OMAP4430_DPLL_DIV_MASK (0x7f << 0) -#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0) -#define OMAP4430_DPLL_EN_MASK (0x7 << 0) -#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10) -#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8) -#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8) -#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) -#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24) #define OMAP4430_DSS_STATDEP_SHIFT 8 #define OMAP4430_DUCATI_STATDEP_SHIFT 0 #define OMAP4430_GFX_STATDEP_SHIFT 10 -#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0) -#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0) -#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0) -#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0) #define OMAP4430_IDLEST_SHIFT 16 #define OMAP4430_IDLEST_MASK (0x3 << 16) #define OMAP4430_IVAHD_STATDEP_SHIFT 2 @@ -98,46 +38,5 @@ #define OMAP4430_MEMIF_STATDEP_SHIFT 4 #define OMAP4430_MODULEMODE_SHIFT 0 #define OMAP4430_MODULEMODE_MASK (0x3 << 0) -#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8 -#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8 -#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8 -#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9 -#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10 -#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15 -#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13 -#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14 -#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11 -#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12 -#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11 -#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10 -#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11 -#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8 -#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9 -#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10 -#define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8 -#define OMAP4430_PAD_CLKS_GATE_SHIFT 8 -#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20 -#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2 -#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22 -#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2 -#define OMAP4430_SCALE_FCLK_SHIFT 0 -#define OMAP4430_SCALE_FCLK_WIDTH 0x1 -#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10 -#define OMAP4430_ST_DPLL_CLK_MASK (1 << 0) -#define OMAP4430_SYS_CLKSEL_SHIFT 0 -#define OMAP4430_SYS_CLKSEL_WIDTH 0x3 #define OMAP4430_TESLA_STATDEP_SHIFT 1 #endif diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h index 1a9725c7ad30..13710cefaf41 100644 --- a/arch/arm/mach-omap2/cm1_44xx.h +++ b/arch/arm/mach-omap2/cm1_44xx.h @@ -34,184 +34,10 @@ #define OMAP4430_CM1_MPU_INST 0x0300 #define OMAP4430_CM1_TESLA_INST 0x0400 #define OMAP4430_CM1_ABE_INST 0x0500 -#define OMAP4430_CM1_RESTORE_INST 0x0e00 -#define OMAP4430_CM1_INSTR_INST 0x0f00 /* CM1 clockdomain register offsets (from instance start) */ #define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000 #define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000 #define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000 -/* CM1 */ - -/* CM1.OCP_SOCKET_CM1 register offsets */ -#define OMAP4_REVISION_CM1_OFFSET 0x0000 -#define OMAP4430_REVISION_CM1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0000) -#define OMAP4_CM_CM1_PROFILING_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_CM1_PROFILING_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_OCP_SOCKET_INST, 0x0040) - -/* CM1.CKGEN_CM1 register offsets */ -#define OMAP4_CM_CLKSEL_CORE_OFFSET 0x0000 -#define OMAP4430_CM_CLKSEL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0000) -#define OMAP4_CM_CLKSEL_ABE_OFFSET 0x0008 -#define OMAP4430_CM_CLKSEL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0008) -#define OMAP4_CM_DLL_CTRL_OFFSET 0x0010 -#define OMAP4430_CM_DLL_CTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0010) -#define OMAP4_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 -#define OMAP4430_CM_CLKMODE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0020) -#define OMAP4_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 -#define OMAP4430_CM_IDLEST_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0024) -#define OMAP4_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 -#define OMAP4430_CM_AUTOIDLE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0028) -#define OMAP4_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c -#define OMAP4430_CM_CLKSEL_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x002c) -#define OMAP4_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 -#define OMAP4430_CM_DIV_M2_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0030) -#define OMAP4_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 -#define OMAP4430_CM_DIV_M3_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0034) -#define OMAP4_CM_DIV_M4_DPLL_CORE_OFFSET 0x0038 -#define OMAP4430_CM_DIV_M4_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0038) -#define OMAP4_CM_DIV_M5_DPLL_CORE_OFFSET 0x003c -#define OMAP4430_CM_DIV_M5_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x003c) -#define OMAP4_CM_DIV_M6_DPLL_CORE_OFFSET 0x0040 -#define OMAP4430_CM_DIV_M6_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0040) -#define OMAP4_CM_DIV_M7_DPLL_CORE_OFFSET 0x0044 -#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c) -#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050 -#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050) -#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 -#define OMAP4430_CM_CLKMODE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0060) -#define OMAP4_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 -#define OMAP4430_CM_IDLEST_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0064) -#define OMAP4_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 -#define OMAP4430_CM_AUTOIDLE_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0068) -#define OMAP4_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c -#define OMAP4430_CM_CLKSEL_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x006c) -#define OMAP4_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 -#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c) -#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c -#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c) -#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 -#define OMAP4430_CM_CLKMODE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a0) -#define OMAP4_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 -#define OMAP4430_CM_IDLEST_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a4) -#define OMAP4_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 -#define OMAP4430_CM_AUTOIDLE_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00a8) -#define OMAP4_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac -#define OMAP4430_CM_CLKSEL_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ac) -#define OMAP4_CM_DIV_M4_DPLL_IVA_OFFSET 0x00b8 -#define OMAP4430_CM_DIV_M4_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00b8) -#define OMAP4_CM_DIV_M5_DPLL_IVA_OFFSET 0x00bc -#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc) -#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc -#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc) -#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 -#define OMAP4430_CM_CLKMODE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e0) -#define OMAP4_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 -#define OMAP4430_CM_IDLEST_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e4) -#define OMAP4_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 -#define OMAP4430_CM_AUTOIDLE_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00e8) -#define OMAP4_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec -#define OMAP4430_CM_CLKSEL_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00ec) -#define OMAP4_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 -#define OMAP4430_CM_DIV_M2_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f0) -#define OMAP4_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 -#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c) -#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120 -#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120) -#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124 -#define OMAP4430_CM_IDLEST_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0124) -#define OMAP4_CM_AUTOIDLE_DPLL_DDRPHY_OFFSET 0x0128 -#define OMAP4430_CM_AUTOIDLE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0128) -#define OMAP4_CM_CLKSEL_DPLL_DDRPHY_OFFSET 0x012c -#define OMAP4430_CM_CLKSEL_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x012c) -#define OMAP4_CM_DIV_M2_DPLL_DDRPHY_OFFSET 0x0130 -#define OMAP4430_CM_DIV_M2_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0130) -#define OMAP4_CM_DIV_M4_DPLL_DDRPHY_OFFSET 0x0138 -#define OMAP4430_CM_DIV_M4_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0138) -#define OMAP4_CM_DIV_M5_DPLL_DDRPHY_OFFSET 0x013c -#define OMAP4430_CM_DIV_M5_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x013c) -#define OMAP4_CM_DIV_M6_DPLL_DDRPHY_OFFSET 0x0140 -#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c) -#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 -#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160) -#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 -#define OMAP4430_CM_SHADOW_FREQ_CONFIG2 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0164) -#define OMAP4_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 -#define OMAP4430_CM_DYN_DEP_PRESCAL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0170) -#define OMAP4_CM_RESTORE_ST_OFFSET 0x0180 -#define OMAP4430_CM_RESTORE_ST OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0180) - -/* CM1.MPU_CM1 register offsets */ -#define OMAP4_CM_MPU_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_MPU_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0000) -#define OMAP4_CM_MPU_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_MPU_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0004) -#define OMAP4_CM_MPU_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_MPU_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0008) -#define OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_MPU_MPU_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_MPU_INST, 0x0020) - -/* CM1.TESLA_CM1 register offsets */ -#define OMAP4_CM_TESLA_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_TESLA_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0000) -#define OMAP4_CM_TESLA_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_TESLA_STATICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0004) -#define OMAP4_CM_TESLA_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_TESLA_DYNAMICDEP OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0008) -#define OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_TESLA_TESLA_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_TESLA_INST, 0x0020) - -/* CM1.ABE_CM1 register offsets */ -#define OMAP4_CM1_ABE_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM1_ABE_CLKSTCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0000) -#define OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM1_ABE_L4ABE_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0020) -#define OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM1_ABE_AESS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0028) -#define OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET 0x0030 -#define OMAP4430_CM1_ABE_PDM_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0030) -#define OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET 0x0038 -#define OMAP4430_CM1_ABE_DMIC_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0038) -#define OMAP4_CM1_ABE_MCASP_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM1_ABE_MCASP_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0040) -#define OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 -#define OMAP4430_CM1_ABE_MCBSP1_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0048) -#define OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 -#define OMAP4430_CM1_ABE_MCBSP2_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0050) -#define OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 -#define OMAP4430_CM1_ABE_MCBSP3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0058) -#define OMAP4_CM1_ABE_SLIMBUS_CLKCTRL_OFFSET 0x0060 -#define OMAP4430_CM1_ABE_SLIMBUS_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0060) -#define OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 -#define OMAP4430_CM1_ABE_TIMER5_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0068) -#define OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 -#define OMAP4430_CM1_ABE_TIMER6_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0070) -#define OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 -#define OMAP4430_CM1_ABE_TIMER7_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0078) -#define OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 -#define OMAP4430_CM1_ABE_TIMER8_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0080) -#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088 -#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088) - #endif diff --git a/arch/arm/mach-omap2/cm1_54xx.h b/arch/arm/mach-omap2/cm1_54xx.h index eb86bbd93f35..fdca20aa49d9 100644 --- a/arch/arm/mach-omap2/cm1_54xx.h +++ b/arch/arm/mach-omap2/cm1_54xx.h @@ -30,178 +30,10 @@ #define OMAP54XX_CM_CORE_AON_MPU_INST 0x0300 #define OMAP54XX_CM_CORE_AON_DSP_INST 0x0400 #define OMAP54XX_CM_CORE_AON_ABE_INST 0x0500 -#define OMAP54XX_CM_CORE_AON_RESTORE_INST 0x0e00 -#define OMAP54XX_CM_CORE_AON_INSTR_INST 0x0f00 /* CM_CORE_AON clockdomain register offsets (from instance start) */ #define OMAP54XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000 #define OMAP54XX_CM_CORE_AON_DSP_DSP_CDOFFS 0x0000 #define OMAP54XX_CM_CORE_AON_ABE_ABE_CDOFFS 0x0000 -/* CM_CORE_AON */ - -/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */ -#define OMAP54XX_REVISION_CM_CORE_AON_OFFSET 0x0000 -#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040 -#define OMAP54XX_CM_CM_CORE_AON_PROFILING_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040) -#define OMAP54XX_CM_CORE_AON_DEBUG_CFG_OFFSET 0x0080 -#define OMAP54XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x0084 -#define OMAP54XX_CM_CORE_AON_DEBUG_MPU_FD_TRANS_OFFSET 0x0090 -#define OMAP54XX_CM_CORE_AON_DEBUG_DSP_FD_TRANS_OFFSET 0x0094 -#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS_OFFSET 0x0098 -#define OMAP54XX_CM_CORE_AON_DEBUG_ABE_FD_TRANS2_OFFSET 0x009c -#define OMAP54XX_CM_CORE_AON_DEBUG_CM_CORE_AON_FD_TRANS_OFFSET 0x00a0 -#define OMAP54XX_CM_CORE_AON_DEBUG_C2C_FD_TRANS_OFFSET 0x00a4 -#define OMAP54XX_CM_CORE_AON_DEBUG_CAM_FD_TRANS_OFFSET 0x00a8 -#define OMAP54XX_CM_CORE_AON_DEBUG_COREAON_FD_TRANS_OFFSET 0x00ac -#define OMAP54XX_CM_CORE_AON_DEBUG_CUSTEFUSE_FD_TRANS_OFFSET 0x00b0 -#define OMAP54XX_CM_CORE_AON_DEBUG_DMA_FD_TRANS_OFFSET 0x00b4 -#define OMAP54XX_CM_CORE_AON_DEBUG_DSS_FD_TRANS_OFFSET 0x00b8 -#define OMAP54XX_CM_CORE_AON_DEBUG_EMIF_FD_TRANS_OFFSET 0x00bc -#define OMAP54XX_CM_CORE_AON_DEBUG_GPU_FD_TRANS_OFFSET 0x00c0 -#define OMAP54XX_CM_CORE_AON_DEBUG_IPU_FD_TRANS_OFFSET 0x00c4 -#define OMAP54XX_CM_CORE_AON_DEBUG_IVA_FD_TRANS_OFFSET 0x00c8 -#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS_OFFSET 0x00cc -#define OMAP54XX_CM_CORE_AON_DEBUG_L3INIT_FD_TRANS2_OFFSET 0x00d0 -#define OMAP54XX_CM_CORE_AON_DEBUG_L3INSTR_FD_TRANS_OFFSET 0x00d4 -#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN1_FD_TRANS_OFFSET 0x00d8 -#define OMAP54XX_CM_CORE_AON_DEBUG_L3MAIN2_FD_TRANS_OFFSET 0x00dc -#define OMAP54XX_CM_CORE_AON_DEBUG_L4CFG_FD_TRANS_OFFSET 0x00e0 -#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS_OFFSET 0x00e4 -#define OMAP54XX_CM_CORE_AON_DEBUG_L4PER_FD_TRANS2_OFFSET 0x00e8 -#define OMAP54XX_CM_CORE_AON_DEBUG_L4SEC_FD_TRANS_OFFSET 0x00ec -#define OMAP54XX_CM_CORE_AON_DEBUG_MIPIEXT_FD_TRANS_OFFSET 0x00f0 - -/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */ -#define OMAP54XX_CM_CLKSEL_CORE_OFFSET 0x0000 -#define OMAP54XX_CM_CLKSEL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0000) -#define OMAP54XX_CM_CLKSEL_ABE_OFFSET 0x0008 -#define OMAP54XX_CM_CLKSEL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0008) -#define OMAP54XX_CM_DLL_CTRL_OFFSET 0x0010 -#define OMAP54XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 -#define OMAP54XX_CM_CLKMODE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0020) -#define OMAP54XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 -#define OMAP54XX_CM_IDLEST_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0024) -#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 -#define OMAP54XX_CM_AUTOIDLE_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0028) -#define OMAP54XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c -#define OMAP54XX_CM_CLKSEL_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x002c) -#define OMAP54XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 -#define OMAP54XX_CM_DIV_M2_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0030) -#define OMAP54XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 -#define OMAP54XX_CM_DIV_M3_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0034) -#define OMAP54XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038 -#define OMAP54XX_CM_DIV_H11_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0038) -#define OMAP54XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c -#define OMAP54XX_CM_DIV_H12_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x003c) -#define OMAP54XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040 -#define OMAP54XX_CM_DIV_H13_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0040) -#define OMAP54XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044 -#define OMAP54XX_CM_DIV_H14_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0044) -#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 -#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c -#define OMAP54XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050 -#define OMAP54XX_CM_DIV_H21_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0050) -#define OMAP54XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054 -#define OMAP54XX_CM_DIV_H22_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0054) -#define OMAP54XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058 -#define OMAP54XX_CM_DIV_H23_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0058) -#define OMAP54XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c -#define OMAP54XX_CM_DIV_H24_DPLL_CORE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x005c) -#define OMAP54XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 -#define OMAP54XX_CM_CLKMODE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0060) -#define OMAP54XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 -#define OMAP54XX_CM_IDLEST_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0064) -#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 -#define OMAP54XX_CM_AUTOIDLE_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0068) -#define OMAP54XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c -#define OMAP54XX_CM_CLKSEL_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x006c) -#define OMAP54XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 -#define OMAP54XX_CM_DIV_M2_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x0070) -#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 -#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c -#define OMAP54XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c -#define OMAP54XX_CM_BYPCLK_DPLL_MPU OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x009c) -#define OMAP54XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 -#define OMAP54XX_CM_CLKMODE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a0) -#define OMAP54XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 -#define OMAP54XX_CM_IDLEST_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a4) -#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 -#define OMAP54XX_CM_AUTOIDLE_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00a8) -#define OMAP54XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac -#define OMAP54XX_CM_CLKSEL_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ac) -#define OMAP54XX_CM_DIV_H11_DPLL_IVA_OFFSET 0x00b8 -#define OMAP54XX_CM_DIV_H11_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00b8) -#define OMAP54XX_CM_DIV_H12_DPLL_IVA_OFFSET 0x00bc -#define OMAP54XX_CM_DIV_H12_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00bc) -#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 -#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc -#define OMAP54XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc -#define OMAP54XX_CM_BYPCLK_DPLL_IVA OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00dc) -#define OMAP54XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 -#define OMAP54XX_CM_CLKMODE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e0) -#define OMAP54XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 -#define OMAP54XX_CM_IDLEST_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e4) -#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 -#define OMAP54XX_CM_AUTOIDLE_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00e8) -#define OMAP54XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec -#define OMAP54XX_CM_CLKSEL_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00ec) -#define OMAP54XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 -#define OMAP54XX_CM_DIV_M2_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f0) -#define OMAP54XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 -#define OMAP54XX_CM_DIV_M3_DPLL_ABE OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_CKGEN_INST, 0x00f4) -#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 -#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c -#define OMAP54XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 -#define OMAP54XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 -#define OMAP54XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 -#define OMAP54XX_CM_RESTORE_ST_OFFSET 0x0180 - -/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */ -#define OMAP54XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 -#define OMAP54XX_CM_MPU_STATICDEP_OFFSET 0x0004 -#define OMAP54XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008 -#define OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 -#define OMAP54XX_CM_MPU_MPU_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0020) -#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028 -#define OMAP54XX_CM_MPU_MPU_MPU_DBG_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_MPU_INST, 0x0028) - -/* CM_CORE_AON.DSP_CM_CORE_AON register offsets */ -#define OMAP54XX_CM_DSP_CLKSTCTRL_OFFSET 0x0000 -#define OMAP54XX_CM_DSP_STATICDEP_OFFSET 0x0004 -#define OMAP54XX_CM_DSP_DYNAMICDEP_OFFSET 0x0008 -#define OMAP54XX_CM_DSP_DSP_CLKCTRL_OFFSET 0x0020 -#define OMAP54XX_CM_DSP_DSP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_DSP_INST, 0x0020) - -/* CM_CORE_AON.ABE_CM_CORE_AON register offsets */ -#define OMAP54XX_CM_ABE_CLKSTCTRL_OFFSET 0x0000 -#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET 0x0020 -#define OMAP54XX_CM_ABE_L4_ABE_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0020) -#define OMAP54XX_CM_ABE_AESS_CLKCTRL_OFFSET 0x0028 -#define OMAP54XX_CM_ABE_AESS_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0028) -#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET 0x0030 -#define OMAP54XX_CM_ABE_MCPDM_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0030) -#define OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET 0x0038 -#define OMAP54XX_CM_ABE_DMIC_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0038) -#define OMAP54XX_CM_ABE_MCASP_CLKCTRL_OFFSET 0x0040 -#define OMAP54XX_CM_ABE_MCASP_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0040) -#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET 0x0048 -#define OMAP54XX_CM_ABE_MCBSP1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0048) -#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET 0x0050 -#define OMAP54XX_CM_ABE_MCBSP2_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0050) -#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET 0x0058 -#define OMAP54XX_CM_ABE_MCBSP3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0058) -#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL_OFFSET 0x0060 -#define OMAP54XX_CM_ABE_SLIMBUS1_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0060) -#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET 0x0068 -#define OMAP54XX_CM_ABE_TIMER5_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0068) -#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET 0x0070 -#define OMAP54XX_CM_ABE_TIMER6_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0070) -#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET 0x0078 -#define OMAP54XX_CM_ABE_TIMER7_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0078) -#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET 0x0080 -#define OMAP54XX_CM_ABE_TIMER8_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0080) -#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL_OFFSET 0x0088 -#define OMAP54XX_CM_ABE_WD_TIMER3_CLKCTRL OMAP54XX_CM_CORE_AON_REGADDR(OMAP54XX_CM_CORE_AON_ABE_INST, 0x0088) - #endif diff --git a/arch/arm/mach-omap2/cm1_7xx.h b/arch/arm/mach-omap2/cm1_7xx.h index aae3831f5233..a543eb3db773 100644 --- a/arch/arm/mach-omap2/cm1_7xx.h +++ b/arch/arm/mach-omap2/cm1_7xx.h @@ -38,8 +38,6 @@ #define DRA7XX_CM_CORE_AON_EVE4_INST 0x0700 #define DRA7XX_CM_CORE_AON_RTC_INST 0x0740 #define DRA7XX_CM_CORE_AON_VPE_INST 0x0760 -#define DRA7XX_CM_CORE_AON_RESTORE_INST 0x0e00 -#define DRA7XX_CM_CORE_AON_INSTR_INST 0x0f00 /* CM_CORE_AON clockdomain register offsets (from instance start) */ #define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000 @@ -54,265 +52,4 @@ #define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS 0x0000 #define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS 0x0000 -/* CM_CORE_AON */ - -/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */ -#define DRA7XX_REVISION_CM_CORE_AON_OFFSET 0x0000 -#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040 -#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040) -#define DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x00ec -#define DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET 0x00f0 -#define DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET 0x00f4 -#define DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET 0x00f8 -#define DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET 0x00fc - -/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */ -#define DRA7XX_CM_CLKSEL_CORE_OFFSET 0x0000 -#define DRA7XX_CM_CLKSEL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000) -#define DRA7XX_CM_CLKSEL_ABE_OFFSET 0x0008 -#define DRA7XX_CM_CLKSEL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008) -#define DRA7XX_CM_DLL_CTRL_OFFSET 0x0010 -#define DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020 -#define DRA7XX_CM_CLKMODE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020) -#define DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024 -#define DRA7XX_CM_IDLEST_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024) -#define DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028 -#define DRA7XX_CM_AUTOIDLE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028) -#define DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c -#define DRA7XX_CM_CLKSEL_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c) -#define DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030 -#define DRA7XX_CM_DIV_M2_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030) -#define DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034 -#define DRA7XX_CM_DIV_M3_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034) -#define DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038 -#define DRA7XX_CM_DIV_H11_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038) -#define DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c -#define DRA7XX_CM_DIV_H12_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c) -#define DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040 -#define DRA7XX_CM_DIV_H13_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040) -#define DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044 -#define DRA7XX_CM_DIV_H14_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044) -#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048 -#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c -#define DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050 -#define DRA7XX_CM_DIV_H21_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050) -#define DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054 -#define DRA7XX_CM_DIV_H22_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054) -#define DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058 -#define DRA7XX_CM_DIV_H23_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058) -#define DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c -#define DRA7XX_CM_DIV_H24_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c) -#define DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060 -#define DRA7XX_CM_CLKMODE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060) -#define DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064 -#define DRA7XX_CM_IDLEST_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064) -#define DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068 -#define DRA7XX_CM_AUTOIDLE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068) -#define DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c -#define DRA7XX_CM_CLKSEL_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c) -#define DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070 -#define DRA7XX_CM_DIV_M2_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070) -#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088 -#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c -#define DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c -#define DRA7XX_CM_BYPCLK_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c) -#define DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0 -#define DRA7XX_CM_CLKMODE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0) -#define DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4 -#define DRA7XX_CM_IDLEST_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4) -#define DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8 -#define DRA7XX_CM_AUTOIDLE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8) -#define DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac -#define DRA7XX_CM_CLKSEL_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac) -#define DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET 0x00b0 -#define DRA7XX_CM_DIV_M2_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0) -#define DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET 0x00b4 -#define DRA7XX_CM_DIV_M3_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4) -#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8 -#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc -#define DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc -#define DRA7XX_CM_BYPCLK_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc) -#define DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0 -#define DRA7XX_CM_CLKMODE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0) -#define DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4 -#define DRA7XX_CM_IDLEST_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4) -#define DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8 -#define DRA7XX_CM_AUTOIDLE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8) -#define DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec -#define DRA7XX_CM_CLKSEL_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec) -#define DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0 -#define DRA7XX_CM_DIV_M2_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0) -#define DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4 -#define DRA7XX_CM_DIV_M3_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4) -#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108 -#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c -#define DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0110 -#define DRA7XX_CM_CLKMODE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110) -#define DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0114 -#define DRA7XX_CM_IDLEST_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114) -#define DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0118 -#define DRA7XX_CM_AUTOIDLE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118) -#define DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x011c -#define DRA7XX_CM_CLKSEL_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c) -#define DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x0120 -#define DRA7XX_CM_DIV_M2_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120) -#define DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET 0x0124 -#define DRA7XX_CM_DIV_M3_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124) -#define DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET 0x0128 -#define DRA7XX_CM_DIV_H11_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128) -#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x012c -#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x0130 -#define DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET 0x0134 -#define DRA7XX_CM_CLKMODE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134) -#define DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET 0x0138 -#define DRA7XX_CM_IDLEST_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138) -#define DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET 0x013c -#define DRA7XX_CM_AUTOIDLE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c) -#define DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET 0x0140 -#define DRA7XX_CM_CLKSEL_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140) -#define DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET 0x0144 -#define DRA7XX_CM_DIV_M2_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144) -#define DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET 0x0148 -#define DRA7XX_CM_DIV_M3_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148) -#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET 0x014c -#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET 0x0150 -#define DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET 0x0154 -#define DRA7XX_CM_BYPCLK_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154) -#define DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160 -#define DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164 -#define DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170 -#define DRA7XX_CM_RESTORE_ST_OFFSET 0x0180 -#define DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET 0x0184 -#define DRA7XX_CM_CLKMODE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184) -#define DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET 0x0188 -#define DRA7XX_CM_IDLEST_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188) -#define DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET 0x018c -#define DRA7XX_CM_AUTOIDLE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c) -#define DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET 0x0190 -#define DRA7XX_CM_CLKSEL_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190) -#define DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET 0x0194 -#define DRA7XX_CM_DIV_M2_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194) -#define DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET 0x0198 -#define DRA7XX_CM_DIV_M3_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198) -#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET 0x019c -#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET 0x01a0 -#define DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET 0x01a4 -#define DRA7XX_CM_BYPCLK_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4) -#define DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET 0x01a8 -#define DRA7XX_CM_CLKMODE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8) -#define DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET 0x01ac -#define DRA7XX_CM_IDLEST_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac) -#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET 0x01b0 -#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0) -#define DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET 0x01b4 -#define DRA7XX_CM_CLKSEL_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4) -#define DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET 0x01b8 -#define DRA7XX_CM_DIV_M2_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8) -#define DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET 0x01bc -#define DRA7XX_CM_DIV_M3_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc) -#define DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET 0x01c0 -#define DRA7XX_CM_DIV_H11_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0) -#define DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET 0x01c4 -#define DRA7XX_CM_DIV_H12_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4) -#define DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET 0x01c8 -#define DRA7XX_CM_DIV_H13_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8) -#define DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET 0x01cc -#define DRA7XX_CM_DIV_H14_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc) -#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET 0x01d0 -#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET 0x01d4 -#define DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET 0x01d8 -#define DRA7XX_CM_CLKMODE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8) -#define DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET 0x01dc -#define DRA7XX_CM_IDLEST_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc) -#define DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET 0x01e0 -#define DRA7XX_CM_AUTOIDLE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0) -#define DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET 0x01e4 -#define DRA7XX_CM_CLKSEL_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4) -#define DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET 0x01e8 -#define DRA7XX_CM_DIV_M2_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8) -#define DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET 0x01ec -#define DRA7XX_CM_DIV_M3_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec) -#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET 0x01f0 -#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET 0x01f4 - -/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */ -#define DRA7XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_MPU_STATICDEP_OFFSET 0x0004 -#define DRA7XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008 -#define DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 -#define DRA7XX_CM_MPU_MPU_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020) -#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028 -#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028) - -/* CM_CORE_AON.DSP1_CM_CORE_AON register offsets */ -#define DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_DSP1_STATICDEP_OFFSET 0x0004 -#define DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET 0x0008 -#define DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET 0x0020 -#define DRA7XX_CM_DSP1_DSP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020) - -/* CM_CORE_AON.IPU_CM_CORE_AON register offsets */ -#define DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_IPU1_STATICDEP_OFFSET 0x0004 -#define DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET 0x0008 -#define DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET 0x0020 -#define DRA7XX_CM_IPU1_IPU1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020) -#define DRA7XX_CM_IPU_CLKSTCTRL_OFFSET 0x0040 -#define DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET 0x0050 -#define DRA7XX_CM_IPU_MCASP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050) -#define DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET 0x0058 -#define DRA7XX_CM_IPU_TIMER5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058) -#define DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET 0x0060 -#define DRA7XX_CM_IPU_TIMER6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060) -#define DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET 0x0068 -#define DRA7XX_CM_IPU_TIMER7_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068) -#define DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET 0x0070 -#define DRA7XX_CM_IPU_TIMER8_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070) -#define DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET 0x0078 -#define DRA7XX_CM_IPU_I2C5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078) -#define DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET 0x0080 -#define DRA7XX_CM_IPU_UART6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080) - -/* CM_CORE_AON.DSP2_CM_CORE_AON register offsets */ -#define DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_DSP2_STATICDEP_OFFSET 0x0004 -#define DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET 0x0008 -#define DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET 0x0020 -#define DRA7XX_CM_DSP2_DSP2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020) - -/* CM_CORE_AON.EVE1_CM_CORE_AON register offsets */ -#define DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_EVE1_STATICDEP_OFFSET 0x0004 -#define DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET 0x0020 -#define DRA7XX_CM_EVE1_EVE1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020) - -/* CM_CORE_AON.EVE2_CM_CORE_AON register offsets */ -#define DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_EVE2_STATICDEP_OFFSET 0x0004 -#define DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET 0x0020 -#define DRA7XX_CM_EVE2_EVE2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020) - -/* CM_CORE_AON.EVE3_CM_CORE_AON register offsets */ -#define DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_EVE3_STATICDEP_OFFSET 0x0004 -#define DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET 0x0020 -#define DRA7XX_CM_EVE3_EVE3_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020) - -/* CM_CORE_AON.EVE4_CM_CORE_AON register offsets */ -#define DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_EVE4_STATICDEP_OFFSET 0x0004 -#define DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET 0x0020 -#define DRA7XX_CM_EVE4_EVE4_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020) - -/* CM_CORE_AON.RTC_CM_CORE_AON register offsets */ -#define DRA7XX_CM_RTC_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET 0x0004 -#define DRA7XX_CM_RTC_RTCSS_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004) - -/* CM_CORE_AON.VPE_CM_CORE_AON register offsets */ -#define DRA7XX_CM_VPE_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET 0x0004 -#define DRA7XX_CM_VPE_VPE_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004) -#define DRA7XX_CM_VPE_STATICDEP_OFFSET 0x0008 - #endif diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h index 370d295446b6..7f9b7a81f153 100644 --- a/arch/arm/mach-omap2/cm2_44xx.h +++ b/arch/arm/mach-omap2/cm2_44xx.h @@ -40,8 +40,6 @@ #define OMAP4430_CM2_L3INIT_INST 0x1300 #define OMAP4430_CM2_L4PER_INST 0x1400 #define OMAP4430_CM2_CEFUSE_INST 0x1600 -#define OMAP4430_CM2_RESTORE_INST 0x1e00 -#define OMAP4430_CM2_INSTR_INST 0x1f00 /* CM2 clockdomain register offsets (from instance start) */ #define OMAP4430_CM2_ALWAYS_ON_ALWON_CDOFFS 0x0000 @@ -62,388 +60,4 @@ #define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180 #define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000 -/* CM2 */ - -/* CM2.OCP_SOCKET_CM2 register offsets */ -#define OMAP4_REVISION_CM2_OFFSET 0x0000 -#define OMAP4430_REVISION_CM2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0000) -#define OMAP4_CM_CM2_PROFILING_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_CM2_PROFILING_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_OCP_SOCKET_INST, 0x0040) - -/* CM2.CKGEN_CM2 register offsets */ -#define OMAP4_CM_CLKSEL_DUCATI_ISS_ROOT_OFFSET 0x0000 -#define OMAP4430_CM_CLKSEL_DUCATI_ISS_ROOT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0000) -#define OMAP4_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 -#define OMAP4430_CM_CLKSEL_USB_60MHZ OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0004) -#define OMAP4_CM_SCALE_FCLK_OFFSET 0x0008 -#define OMAP4430_CM_SCALE_FCLK OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0008) -#define OMAP4_CM_CORE_DVFS_PERF1_OFFSET 0x0010 -#define OMAP4430_CM_CORE_DVFS_PERF1 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0010) -#define OMAP4_CM_CORE_DVFS_PERF2_OFFSET 0x0014 -#define OMAP4430_CM_CORE_DVFS_PERF2 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0014) -#define OMAP4_CM_CORE_DVFS_PERF3_OFFSET 0x0018 -#define OMAP4430_CM_CORE_DVFS_PERF3 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0018) -#define OMAP4_CM_CORE_DVFS_PERF4_OFFSET 0x001c -#define OMAP4430_CM_CORE_DVFS_PERF4 OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x001c) -#define OMAP4_CM_CORE_DVFS_CURRENT_OFFSET 0x0024 -#define OMAP4430_CM_CORE_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0024) -#define OMAP4_CM_IVA_DVFS_PERF_TESLA_OFFSET 0x0028 -#define OMAP4430_CM_IVA_DVFS_PERF_TESLA OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0028) -#define OMAP4_CM_IVA_DVFS_PERF_IVAHD_OFFSET 0x002c -#define OMAP4430_CM_IVA_DVFS_PERF_IVAHD OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x002c) -#define OMAP4_CM_IVA_DVFS_PERF_ABE_OFFSET 0x0030 -#define OMAP4430_CM_IVA_DVFS_PERF_ABE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0030) -#define OMAP4_CM_IVA_DVFS_CURRENT_OFFSET 0x0038 -#define OMAP4430_CM_IVA_DVFS_CURRENT OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0038) -#define OMAP4_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 -#define OMAP4430_CM_CLKMODE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0040) -#define OMAP4_CM_IDLEST_DPLL_PER_OFFSET 0x0044 -#define OMAP4430_CM_IDLEST_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0044) -#define OMAP4_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 -#define OMAP4430_CM_AUTOIDLE_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0048) -#define OMAP4_CM_CLKSEL_DPLL_PER_OFFSET 0x004c -#define OMAP4430_CM_CLKSEL_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x004c) -#define OMAP4_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 -#define OMAP4430_CM_DIV_M2_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0050) -#define OMAP4_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 -#define OMAP4430_CM_DIV_M3_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0054) -#define OMAP4_CM_DIV_M4_DPLL_PER_OFFSET 0x0058 -#define OMAP4430_CM_DIV_M4_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0058) -#define OMAP4_CM_DIV_M5_DPLL_PER_OFFSET 0x005c -#define OMAP4430_CM_DIV_M5_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x005c) -#define OMAP4_CM_DIV_M6_DPLL_PER_OFFSET 0x0060 -#define OMAP4430_CM_DIV_M6_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0060) -#define OMAP4_CM_DIV_M7_DPLL_PER_OFFSET 0x0064 -#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c) -#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 -#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080) -#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084 -#define OMAP4430_CM_IDLEST_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0084) -#define OMAP4_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 -#define OMAP4430_CM_AUTOIDLE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0088) -#define OMAP4_CM_CLKSEL_DPLL_USB_OFFSET 0x008c -#define OMAP4430_CM_CLKSEL_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x008c) -#define OMAP4_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 -#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac) -#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 -#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4) -#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0 -#define OMAP4430_CM_CLKMODE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c0) -#define OMAP4_CM_IDLEST_DPLL_UNIPRO_OFFSET 0x00c4 -#define OMAP4430_CM_IDLEST_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c4) -#define OMAP4_CM_AUTOIDLE_DPLL_UNIPRO_OFFSET 0x00c8 -#define OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00c8) -#define OMAP4_CM_CLKSEL_DPLL_UNIPRO_OFFSET 0x00cc -#define OMAP4430_CM_CLKSEL_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00cc) -#define OMAP4_CM_DIV_M2_DPLL_UNIPRO_OFFSET 0x00d0 -#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0) -#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8 -#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8) -#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec -#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec) - -/* CM2.ALWAYS_ON_CM2 register offsets */ -#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_ALWON_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0000) -#define OMAP4_CM_ALWON_MDMINTC_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_ALWON_MDMINTC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0020) -#define OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_ALWON_SR_MPU_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0028) -#define OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET 0x0030 -#define OMAP4430_CM_ALWON_SR_IVA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0030) -#define OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET 0x0038 -#define OMAP4430_CM_ALWON_SR_CORE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0038) -#define OMAP4_CM_ALWON_USBPHY_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_ALWON_USBPHY_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_ALWAYS_ON_INST, 0x0040) - -/* CM2.CORE_CM2 register offsets */ -#define OMAP4_CM_L3_1_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_L3_1_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0000) -#define OMAP4_CM_L3_1_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_L3_1_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0008) -#define OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_L3_1_L3_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0020) -#define OMAP4_CM_L3_2_CLKSTCTRL_OFFSET 0x0100 -#define OMAP4430_CM_L3_2_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0100) -#define OMAP4_CM_L3_2_DYNAMICDEP_OFFSET 0x0108 -#define OMAP4430_CM_L3_2_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0108) -#define OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET 0x0120 -#define OMAP4430_CM_L3_2_L3_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0120) -#define OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET 0x0128 -#define OMAP4430_CM_L3_2_GPMC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0128) -#define OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 -#define OMAP4430_CM_L3_2_OCMC_RAM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0130) -#define OMAP4_CM_DUCATI_CLKSTCTRL_OFFSET 0x0200 -#define OMAP4430_CM_DUCATI_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0200) -#define OMAP4_CM_DUCATI_STATICDEP_OFFSET 0x0204 -#define OMAP4430_CM_DUCATI_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0204) -#define OMAP4_CM_DUCATI_DYNAMICDEP_OFFSET 0x0208 -#define OMAP4430_CM_DUCATI_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0208) -#define OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET 0x0220 -#define OMAP4430_CM_DUCATI_DUCATI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0220) -#define OMAP4_CM_SDMA_CLKSTCTRL_OFFSET 0x0300 -#define OMAP4430_CM_SDMA_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0300) -#define OMAP4_CM_SDMA_STATICDEP_OFFSET 0x0304 -#define OMAP4430_CM_SDMA_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0304) -#define OMAP4_CM_SDMA_DYNAMICDEP_OFFSET 0x0308 -#define OMAP4430_CM_SDMA_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0308) -#define OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET 0x0320 -#define OMAP4430_CM_SDMA_SDMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0320) -#define OMAP4_CM_MEMIF_CLKSTCTRL_OFFSET 0x0400 -#define OMAP4430_CM_MEMIF_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0400) -#define OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET 0x0420 -#define OMAP4430_CM_MEMIF_DMM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0420) -#define OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET 0x0428 -#define OMAP4430_CM_MEMIF_EMIF_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0428) -#define OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET 0x0430 -#define OMAP4430_CM_MEMIF_EMIF_1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0430) -#define OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET 0x0438 -#define OMAP4430_CM_MEMIF_EMIF_2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0438) -#define OMAP4_CM_MEMIF_DLL_CLKCTRL_OFFSET 0x0440 -#define OMAP4430_CM_MEMIF_DLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0440) -#define OMAP4_CM_MEMIF_EMIF_H1_CLKCTRL_OFFSET 0x0450 -#define OMAP4430_CM_MEMIF_EMIF_H1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0450) -#define OMAP4_CM_MEMIF_EMIF_H2_CLKCTRL_OFFSET 0x0458 -#define OMAP4430_CM_MEMIF_EMIF_H2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0458) -#define OMAP4_CM_MEMIF_DLL_H_CLKCTRL_OFFSET 0x0460 -#define OMAP4430_CM_MEMIF_DLL_H_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0460) -#define OMAP4_CM_D2D_CLKSTCTRL_OFFSET 0x0500 -#define OMAP4430_CM_D2D_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0500) -#define OMAP4_CM_D2D_STATICDEP_OFFSET 0x0504 -#define OMAP4430_CM_D2D_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0504) -#define OMAP4_CM_D2D_DYNAMICDEP_OFFSET 0x0508 -#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508) -#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520 -#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520) -#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528 -#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528) -#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530 -#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530) -#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 -#define OMAP4430_CM_L4CFG_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0600) -#define OMAP4_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 -#define OMAP4430_CM_L4CFG_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0608) -#define OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 -#define OMAP4430_CM_L4CFG_L4_CFG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0620) -#define OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET 0x0628 -#define OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0628) -#define OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 -#define OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0630) -#define OMAP4_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 -#define OMAP4430_CM_L4CFG_SAR_ROM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0638) -#define OMAP4_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 -#define OMAP4430_CM_L3INSTR_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0700) -#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET 0x0720 -#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0720) -#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 -#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0728) -#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET 0x0740 -#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0740) - -/* CM2.IVAHD_CM2 register offsets */ -#define OMAP4_CM_IVAHD_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_IVAHD_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0000) -#define OMAP4_CM_IVAHD_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_IVAHD_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0004) -#define OMAP4_CM_IVAHD_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_IVAHD_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0008) -#define OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_IVAHD_IVAHD_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0020) -#define OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_IVAHD_SL2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_IVAHD_INST, 0x0028) - -/* CM2.CAM_CM2 register offsets */ -#define OMAP4_CM_CAM_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_CAM_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0000) -#define OMAP4_CM_CAM_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_CAM_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0004) -#define OMAP4_CM_CAM_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_CAM_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0008) -#define OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_CAM_ISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0020) -#define OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_CAM_FDIF_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CAM_INST, 0x0028) - -/* CM2.DSS_CM2 register offsets */ -#define OMAP4_CM_DSS_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_DSS_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0000) -#define OMAP4_CM_DSS_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_DSS_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0004) -#define OMAP4_CM_DSS_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_DSS_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0008) -#define OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_DSS_DSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0020) -#define OMAP4_CM_DSS_DEISS_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_DSS_DEISS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_DSS_INST, 0x0028) - -/* CM2.GFX_CM2 register offsets */ -#define OMAP4_CM_GFX_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_GFX_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0000) -#define OMAP4_CM_GFX_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_GFX_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0004) -#define OMAP4_CM_GFX_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_GFX_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0008) -#define OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_GFX_GFX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_GFX_INST, 0x0020) - -/* CM2.L3INIT_CM2 register offsets */ -#define OMAP4_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_L3INIT_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0000) -#define OMAP4_CM_L3INIT_STATICDEP_OFFSET 0x0004 -#define OMAP4430_CM_L3INIT_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0004) -#define OMAP4_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_L3INIT_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0008) -#define OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_L3INIT_MMC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0028) -#define OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 -#define OMAP4430_CM_L3INIT_MMC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0030) -#define OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 -#define OMAP4430_CM_L3INIT_HSI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0038) -#define OMAP4_CM_L3INIT_UNIPRO1_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_L3INIT_UNIPRO1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0040) -#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET 0x0058 -#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0058) -#define OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET 0x0060 -#define OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0060) -#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET 0x0068 -#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0068) -#define OMAP4_CM_L3INIT_P1500_CLKCTRL_OFFSET 0x0078 -#define OMAP4430_CM_L3INIT_P1500_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0078) -#define OMAP4_CM_L3INIT_EMAC_CLKCTRL_OFFSET 0x0080 -#define OMAP4430_CM_L3INIT_EMAC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0080) -#define OMAP4_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 -#define OMAP4430_CM_L3INIT_SATA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0088) -#define OMAP4_CM_L3INIT_TPPSS_CLKCTRL_OFFSET 0x0090 -#define OMAP4430_CM_L3INIT_TPPSS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0090) -#define OMAP4_CM_L3INIT_PCIESS_CLKCTRL_OFFSET 0x0098 -#define OMAP4430_CM_L3INIT_PCIESS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x0098) -#define OMAP4_CM_L3INIT_CCPTX_CLKCTRL_OFFSET 0x00a8 -#define OMAP4430_CM_L3INIT_CCPTX_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00a8) -#define OMAP4_CM_L3INIT_XHPI_CLKCTRL_OFFSET 0x00c0 -#define OMAP4430_CM_L3INIT_XHPI_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c0) -#define OMAP4_CM_L3INIT_MMC6_CLKCTRL_OFFSET 0x00c8 -#define OMAP4430_CM_L3INIT_MMC6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00c8) -#define OMAP4_CM_L3INIT_USB_HOST_FS_CLKCTRL_OFFSET 0x00d0 -#define OMAP4430_CM_L3INIT_USB_HOST_FS_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00d0) -#define OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET 0x00e0 -#define OMAP4430_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L3INIT_INST, 0x00e0) - -/* CM2.L4PER_CM2 register offsets */ -#define OMAP4_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_L4PER_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0000) -#define OMAP4_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_L4PER_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0008) -#define OMAP4_CM_L4PER_ADC_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_L4PER_ADC_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0020) -#define OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0028) -#define OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET 0x0030 -#define OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0030) -#define OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET 0x0038 -#define OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0038) -#define OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0040) -#define OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET 0x0048 -#define OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0048) -#define OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET 0x0050 -#define OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0050) -#define OMAP4_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 -#define OMAP4430_CM_L4PER_ELM_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0058) -#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 -#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0060) -#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 -#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0068) -#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 -#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0070) -#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 -#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0078) -#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 -#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0080) -#define OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 -#define OMAP4430_CM_L4PER_HDQ1W_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0088) -#define OMAP4_CM_L4PER_HECC1_CLKCTRL_OFFSET 0x0090 -#define OMAP4430_CM_L4PER_HECC1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0090) -#define OMAP4_CM_L4PER_HECC2_CLKCTRL_OFFSET 0x0098 -#define OMAP4430_CM_L4PER_HECC2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0098) -#define OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 -#define OMAP4430_CM_L4PER_I2C1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a0) -#define OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 -#define OMAP4430_CM_L4PER_I2C2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00a8) -#define OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 -#define OMAP4430_CM_L4PER_I2C3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b0) -#define OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 -#define OMAP4430_CM_L4PER_I2C4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00b8) -#define OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET 0x00c0 -#define OMAP4430_CM_L4PER_L4PER_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00c0) -#define OMAP4_CM_L4PER_MCASP2_CLKCTRL_OFFSET 0x00d0 -#define OMAP4430_CM_L4PER_MCASP2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d0) -#define OMAP4_CM_L4PER_MCASP3_CLKCTRL_OFFSET 0x00d8 -#define OMAP4430_CM_L4PER_MCASP3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00d8) -#define OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET 0x00e0 -#define OMAP4430_CM_L4PER_MCBSP4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e0) -#define OMAP4_CM_L4PER_MGATE_CLKCTRL_OFFSET 0x00e8 -#define OMAP4430_CM_L4PER_MGATE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00e8) -#define OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 -#define OMAP4430_CM_L4PER_MCSPI1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f0) -#define OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 -#define OMAP4430_CM_L4PER_MCSPI2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x00f8) -#define OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 -#define OMAP4430_CM_L4PER_MCSPI3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0100) -#define OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 -#define OMAP4430_CM_L4PER_MCSPI4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0108) -#define OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET 0x0120 -#define OMAP4430_CM_L4PER_MMCSD3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0120) -#define OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET 0x0128 -#define OMAP4430_CM_L4PER_MMCSD4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0128) -#define OMAP4_CM_L4PER_MSPROHG_CLKCTRL_OFFSET 0x0130 -#define OMAP4430_CM_L4PER_MSPROHG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0130) -#define OMAP4_CM_L4PER_SLIMBUS2_CLKCTRL_OFFSET 0x0138 -#define OMAP4430_CM_L4PER_SLIMBUS2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0138) -#define OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 -#define OMAP4430_CM_L4PER_UART1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0140) -#define OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 -#define OMAP4430_CM_L4PER_UART2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0148) -#define OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 -#define OMAP4430_CM_L4PER_UART3_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0150) -#define OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 -#define OMAP4430_CM_L4PER_UART4_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0158) -#define OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET 0x0160 -#define OMAP4430_CM_L4PER_MMCSD5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0160) -#define OMAP4_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0168 -#define OMAP4430_CM_L4PER_I2C5_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0168) -#define OMAP4_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 -#define OMAP4430_CM_L4SEC_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0180) -#define OMAP4_CM_L4SEC_STATICDEP_OFFSET 0x0184 -#define OMAP4430_CM_L4SEC_STATICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0184) -#define OMAP4_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 -#define OMAP4430_CM_L4SEC_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x0188) -#define OMAP4_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 -#define OMAP4430_CM_L4SEC_AES1_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a0) -#define OMAP4_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 -#define OMAP4430_CM_L4SEC_AES2_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01a8) -#define OMAP4_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 -#define OMAP4430_CM_L4SEC_DES3DES_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b0) -#define OMAP4_CM_L4SEC_PKAEIP29_CLKCTRL_OFFSET 0x01b8 -#define OMAP4430_CM_L4SEC_PKAEIP29_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01b8) -#define OMAP4_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 -#define OMAP4430_CM_L4SEC_RNG_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c0) -#define OMAP4_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 -#define OMAP4430_CM_L4SEC_SHA2MD51_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01c8) -#define OMAP4_CM_L4SEC_CRYPTODMA_CLKCTRL_OFFSET 0x01d8 -#define OMAP4430_CM_L4SEC_CRYPTODMA_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_L4PER_INST, 0x01d8) - -/* CM2.CEFUSE_CM2 register offsets */ -#define OMAP4_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_CEFUSE_CLKSTCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0000) -#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020) - #endif diff --git a/arch/arm/mach-omap2/cm2_54xx.h b/arch/arm/mach-omap2/cm2_54xx.h index 8e49765cd441..7e5860578ae3 100644 --- a/arch/arm/mach-omap2/cm2_54xx.h +++ b/arch/arm/mach-omap2/cm2_54xx.h @@ -35,8 +35,6 @@ #define OMAP54XX_CM_CORE_GPU_INST 0x1500 #define OMAP54XX_CM_CORE_L3INIT_INST 0x1600 #define OMAP54XX_CM_CORE_CUSTEFUSE_INST 0x1700 -#define OMAP54XX_CM_CORE_RESTORE_INST 0x1e00 -#define OMAP54XX_CM_CORE_INSTR_INST 0x1f00 /* CM_CORE clockdomain register offsets (from instance start) */ #define OMAP54XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 @@ -58,327 +56,4 @@ #define OMAP54XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000 #define OMAP54XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000 -/* CM_CORE */ - -/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */ -#define OMAP54XX_REVISION_CM_CORE_OFFSET 0x0000 -#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040 -#define OMAP54XX_CM_CM_CORE_PROFILING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_OCP_SOCKET_INST, 0x0040) -#define OMAP54XX_CM_CORE_DEBUG_CFG_OFFSET 0x0080 -#define OMAP54XX_CM_CORE_DEBUG_OUT_OFFSET 0x0084 - -/* CM_CORE.CKGEN_CM_CORE register offsets */ -#define OMAP54XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0004 -#define OMAP54XX_CM_CLKSEL_USB_60MHZ OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0004) -#define OMAP54XX_CM_CLKMODE_DPLL_PER_OFFSET 0x0040 -#define OMAP54XX_CM_CLKMODE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0040) -#define OMAP54XX_CM_IDLEST_DPLL_PER_OFFSET 0x0044 -#define OMAP54XX_CM_IDLEST_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0044) -#define OMAP54XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0048 -#define OMAP54XX_CM_AUTOIDLE_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0048) -#define OMAP54XX_CM_CLKSEL_DPLL_PER_OFFSET 0x004c -#define OMAP54XX_CM_CLKSEL_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x004c) -#define OMAP54XX_CM_DIV_M2_DPLL_PER_OFFSET 0x0050 -#define OMAP54XX_CM_DIV_M2_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0050) -#define OMAP54XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0054 -#define OMAP54XX_CM_DIV_M3_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0054) -#define OMAP54XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0058 -#define OMAP54XX_CM_DIV_H11_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0058) -#define OMAP54XX_CM_DIV_H12_DPLL_PER_OFFSET 0x005c -#define OMAP54XX_CM_DIV_H12_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x005c) -#define OMAP54XX_CM_DIV_H13_DPLL_PER_OFFSET 0x0060 -#define OMAP54XX_CM_DIV_H13_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0060) -#define OMAP54XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0064 -#define OMAP54XX_CM_DIV_H14_DPLL_PER OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0064) -#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068 -#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c -#define OMAP54XX_CM_CLKMODE_DPLL_USB_OFFSET 0x0080 -#define OMAP54XX_CM_CLKMODE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0080) -#define OMAP54XX_CM_IDLEST_DPLL_USB_OFFSET 0x0084 -#define OMAP54XX_CM_IDLEST_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0084) -#define OMAP54XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0088 -#define OMAP54XX_CM_AUTOIDLE_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0088) -#define OMAP54XX_CM_CLKSEL_DPLL_USB_OFFSET 0x008c -#define OMAP54XX_CM_CLKSEL_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x008c) -#define OMAP54XX_CM_DIV_M2_DPLL_USB_OFFSET 0x0090 -#define OMAP54XX_CM_DIV_M2_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0090) -#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8 -#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac -#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4 -#define OMAP54XX_CM_CLKDCOLDO_DPLL_USB OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00b4) -#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2_OFFSET 0x00c0 -#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c0) -#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2_OFFSET 0x00c4 -#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c4) -#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2_OFFSET 0x00c8 -#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00c8) -#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2_OFFSET 0x00cc -#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00cc) -#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2_OFFSET 0x00d0 -#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00d0) -#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO2_OFFSET 0x00e8 -#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO2_OFFSET 0x00ec -#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2_OFFSET 0x00f4 -#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO2 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x00f4) -#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1_OFFSET 0x0100 -#define OMAP54XX_CM_CLKMODE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0100) -#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1_OFFSET 0x0104 -#define OMAP54XX_CM_IDLEST_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0104) -#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1_OFFSET 0x0108 -#define OMAP54XX_CM_AUTOIDLE_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0108) -#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1_OFFSET 0x010c -#define OMAP54XX_CM_CLKSEL_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x010c) -#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1_OFFSET 0x0110 -#define OMAP54XX_CM_DIV_M2_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0110) -#define OMAP54XX_CM_SSC_DELTAMSTEP_DPLL_UNIPRO1_OFFSET 0x0128 -#define OMAP54XX_CM_SSC_MODFREQDIV_DPLL_UNIPRO1_OFFSET 0x012c -#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1_OFFSET 0x0134 -#define OMAP54XX_CM_CLKDCOLDO_DPLL_UNIPRO1 OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CKGEN_INST, 0x0134) - -/* CM_CORE.COREAON_CM_CORE register offsets */ -#define OMAP54XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000 -#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028 -#define OMAP54XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0028) -#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL_OFFSET 0x0030 -#define OMAP54XX_CM_COREAON_SMARTREFLEX_MM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0030) -#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038 -#define OMAP54XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0038) -#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL_OFFSET 0x0040 -#define OMAP54XX_CM_COREAON_USB_PHY_CORE_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0040) -#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050 -#define OMAP54XX_CM_COREAON_IO_SRCOMP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_COREAON_INST, 0x0050) - -/* CM_CORE.CORE_CM_CORE register offsets */ -#define OMAP54XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000 -#define OMAP54XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008 -#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020 -#define OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0020) -#define OMAP54XX_CM_L3MAIN2_CLKSTCTRL_OFFSET 0x0100 -#define OMAP54XX_CM_L3MAIN2_DYNAMICDEP_OFFSET 0x0108 -#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET 0x0120 -#define OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0120) -#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL_OFFSET 0x0128 -#define OMAP54XX_CM_L3MAIN2_GPMC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0128) -#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL_OFFSET 0x0130 -#define OMAP54XX_CM_L3MAIN2_OCMC_RAM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0130) -#define OMAP54XX_CM_IPU_CLKSTCTRL_OFFSET 0x0200 -#define OMAP54XX_CM_IPU_STATICDEP_OFFSET 0x0204 -#define OMAP54XX_CM_IPU_DYNAMICDEP_OFFSET 0x0208 -#define OMAP54XX_CM_IPU_IPU_CLKCTRL_OFFSET 0x0220 -#define OMAP54XX_CM_IPU_IPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0220) -#define OMAP54XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300 -#define OMAP54XX_CM_DMA_STATICDEP_OFFSET 0x0304 -#define OMAP54XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308 -#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320 -#define OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0320) -#define OMAP54XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400 -#define OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420 -#define OMAP54XX_CM_EMIF_DMM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0420) -#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428 -#define OMAP54XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0428) -#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430 -#define OMAP54XX_CM_EMIF_EMIF1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0430) -#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438 -#define OMAP54XX_CM_EMIF_EMIF2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0438) -#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440 -#define OMAP54XX_CM_EMIF_EMIF_DLL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0440) -#define OMAP54XX_CM_C2C_CLKSTCTRL_OFFSET 0x0500 -#define OMAP54XX_CM_C2C_STATICDEP_OFFSET 0x0504 -#define OMAP54XX_CM_C2C_DYNAMICDEP_OFFSET 0x0508 -#define OMAP54XX_CM_C2C_C2C_CLKCTRL_OFFSET 0x0520 -#define OMAP54XX_CM_C2C_C2C_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0520) -#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL_OFFSET 0x0528 -#define OMAP54XX_CM_C2C_MODEM_ICR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0528) -#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL_OFFSET 0x0530 -#define OMAP54XX_CM_C2C_C2C_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0530) -#define OMAP54XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 -#define OMAP54XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 -#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 -#define OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0620) -#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628 -#define OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0628) -#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET 0x0630 -#define OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0630) -#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 -#define OMAP54XX_CM_L4CFG_SAR_ROM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0638) -#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640 -#define OMAP54XX_CM_L4CFG_OCP2SCP2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0640) -#define OMAP54XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 -#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET 0x0720 -#define OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0720) -#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 -#define OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0728) -#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740 -#define OMAP54XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0740) -#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748 -#define OMAP54XX_CM_L3INSTR_DLL_AGING_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0748) -#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750 -#define OMAP54XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0750) -#define OMAP54XX_CM_MIPIEXT_CLKSTCTRL_OFFSET 0x0800 -#define OMAP54XX_CM_MIPIEXT_STATICDEP_OFFSET 0x0804 -#define OMAP54XX_CM_MIPIEXT_DYNAMICDEP_OFFSET 0x0808 -#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL_OFFSET 0x0820 -#define OMAP54XX_CM_MIPIEXT_LLI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0820) -#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL_OFFSET 0x0828 -#define OMAP54XX_CM_MIPIEXT_LLI_OCP_FW_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0828) -#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL_OFFSET 0x0830 -#define OMAP54XX_CM_MIPIEXT_MPHY_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0830) -#define OMAP54XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0900 -#define OMAP54XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0908 -#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0928 -#define OMAP54XX_CM_L4PER_TIMER10_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0928) -#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0930 -#define OMAP54XX_CM_L4PER_TIMER11_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0930) -#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0938 -#define OMAP54XX_CM_L4PER_TIMER2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0938) -#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0940 -#define OMAP54XX_CM_L4PER_TIMER3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0940) -#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0948 -#define OMAP54XX_CM_L4PER_TIMER4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0948) -#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0950 -#define OMAP54XX_CM_L4PER_TIMER9_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0950) -#define OMAP54XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0958 -#define OMAP54XX_CM_L4PER_ELM_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0958) -#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0960 -#define OMAP54XX_CM_L4PER_GPIO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0960) -#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0968 -#define OMAP54XX_CM_L4PER_GPIO3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0968) -#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0970 -#define OMAP54XX_CM_L4PER_GPIO4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0970) -#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0978 -#define OMAP54XX_CM_L4PER_GPIO5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0978) -#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0980 -#define OMAP54XX_CM_L4PER_GPIO6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0980) -#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0988 -#define OMAP54XX_CM_L4PER_HDQ1W_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0988) -#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x09a0 -#define OMAP54XX_CM_L4PER_I2C1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a0) -#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x09a8 -#define OMAP54XX_CM_L4PER_I2C2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09a8) -#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x09b0 -#define OMAP54XX_CM_L4PER_I2C3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b0) -#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x09b8 -#define OMAP54XX_CM_L4PER_I2C4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09b8) -#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET 0x09c0 -#define OMAP54XX_CM_L4PER_L4_PER_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09c0) -#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x09f0 -#define OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f0) -#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x09f8 -#define OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x09f8) -#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0a00 -#define OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a00) -#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0a08 -#define OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a08) -#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0a10 -#define OMAP54XX_CM_L4PER_GPIO7_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a10) -#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0a18 -#define OMAP54XX_CM_L4PER_GPIO8_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a18) -#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0a20 -#define OMAP54XX_CM_L4PER_MMC3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a20) -#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0a28 -#define OMAP54XX_CM_L4PER_MMC4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a28) -#define OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0a40 -#define OMAP54XX_CM_L4PER_UART1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a40) -#define OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0a48 -#define OMAP54XX_CM_L4PER_UART2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a48) -#define OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0a50 -#define OMAP54XX_CM_L4PER_UART3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a50) -#define OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0a58 -#define OMAP54XX_CM_L4PER_UART4_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a58) -#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET 0x0a60 -#define OMAP54XX_CM_L4PER_MMC5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a60) -#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET 0x0a68 -#define OMAP54XX_CM_L4PER_I2C5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a68) -#define OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0a70 -#define OMAP54XX_CM_L4PER_UART5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a70) -#define OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET 0x0a78 -#define OMAP54XX_CM_L4PER_UART6_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0a78) -#define OMAP54XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0a80 -#define OMAP54XX_CM_L4SEC_STATICDEP_OFFSET 0x0a84 -#define OMAP54XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0a88 -#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x0aa0 -#define OMAP54XX_CM_L4SEC_AES1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa0) -#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x0aa8 -#define OMAP54XX_CM_L4SEC_AES2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0aa8) -#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x0ab0 -#define OMAP54XX_CM_L4SEC_DES3DES_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab0) -#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x0ab8 -#define OMAP54XX_CM_L4SEC_FPKA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ab8) -#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x0ac0 -#define OMAP54XX_CM_L4SEC_RNG_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac0) -#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL_OFFSET 0x0ac8 -#define OMAP54XX_CM_L4SEC_SHA2MD5_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ac8) -#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x0ad8 -#define OMAP54XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CORE_INST, 0x0ad8) - -/* CM_CORE.IVA_CM_CORE register offsets */ -#define OMAP54XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000 -#define OMAP54XX_CM_IVA_STATICDEP_OFFSET 0x0004 -#define OMAP54XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008 -#define OMAP54XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020 -#define OMAP54XX_CM_IVA_IVA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0020) -#define OMAP54XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028 -#define OMAP54XX_CM_IVA_SL2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_IVA_INST, 0x0028) - -/* CM_CORE.CAM_CM_CORE register offsets */ -#define OMAP54XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000 -#define OMAP54XX_CM_CAM_STATICDEP_OFFSET 0x0004 -#define OMAP54XX_CM_CAM_DYNAMICDEP_OFFSET 0x0008 -#define OMAP54XX_CM_CAM_ISS_CLKCTRL_OFFSET 0x0020 -#define OMAP54XX_CM_CAM_ISS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0020) -#define OMAP54XX_CM_CAM_FDIF_CLKCTRL_OFFSET 0x0028 -#define OMAP54XX_CM_CAM_FDIF_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0028) -#define OMAP54XX_CM_CAM_CAL_CLKCTRL_OFFSET 0x0030 -#define OMAP54XX_CM_CAM_CAL_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CAM_INST, 0x0030) - -/* CM_CORE.DSS_CM_CORE register offsets */ -#define OMAP54XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000 -#define OMAP54XX_CM_DSS_STATICDEP_OFFSET 0x0004 -#define OMAP54XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008 -#define OMAP54XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 -#define OMAP54XX_CM_DSS_DSS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0020) -#define OMAP54XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030 -#define OMAP54XX_CM_DSS_BB2D_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_DSS_INST, 0x0030) - -/* CM_CORE.GPU_CM_CORE register offsets */ -#define OMAP54XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000 -#define OMAP54XX_CM_GPU_STATICDEP_OFFSET 0x0004 -#define OMAP54XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008 -#define OMAP54XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020 -#define OMAP54XX_CM_GPU_GPU_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_GPU_INST, 0x0020) - -/* CM_CORE.L3INIT_CM_CORE register offsets */ -#define OMAP54XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 -#define OMAP54XX_CM_L3INIT_STATICDEP_OFFSET 0x0004 -#define OMAP54XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 -#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 -#define OMAP54XX_CM_L3INIT_MMC1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0028) -#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 -#define OMAP54XX_CM_L3INIT_MMC2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0030) -#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL_OFFSET 0x0038 -#define OMAP54XX_CM_L3INIT_HSI_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0038) -#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL_OFFSET 0x0040 -#define OMAP54XX_CM_L3INIT_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0040) -#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL_OFFSET 0x0048 -#define OMAP54XX_CM_L3INIT_MPHY_UNIPRO2_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0048) -#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET 0x0058 -#define OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0058) -#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET 0x0068 -#define OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0068) -#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078 -#define OMAP54XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0078) -#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 -#define OMAP54XX_CM_L3INIT_SATA_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x0088) -#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0 -#define OMAP54XX_CM_L3INIT_OCP2SCP1_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e0) -#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8 -#define OMAP54XX_CM_L3INIT_OCP2SCP3_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00e8) -#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET 0x00f0 -#define OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_L3INIT_INST, 0x00f0) - -/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */ -#define OMAP54XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000 -#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020 -#define OMAP54XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL OMAP54XX_CM_CORE_REGADDR(OMAP54XX_CM_CORE_CUSTEFUSE_INST, 0x0020) - #endif diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h index f8734605b1e1..af63b4b877b2 100644 --- a/arch/arm/mach-omap2/cm2_7xx.h +++ b/arch/arm/mach-omap2/cm2_7xx.h @@ -37,7 +37,6 @@ #define DRA7XX_CM_CORE_L3INIT_INST 0x1300 #define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600 #define DRA7XX_CM_CORE_L4PER_INST 0x1700 -#define DRA7XX_CM_CORE_RESTORE_INST 0x1e18 /* CM_CORE clockdomain register offsets (from instance start) */ #define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000 @@ -61,452 +60,4 @@ #define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc #define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210 -/* CM_CORE */ - -/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */ -#define DRA7XX_REVISION_CM_CORE_OFFSET 0x0000 -#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040 -#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040) -#define DRA7XX_CM_CORE_DEBUG_CFG_OFFSET 0x00f0 - -/* CM_CORE.CKGEN_CM_CORE register offsets */ -#define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0000 -#define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000) -#define DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET 0x003c -#define DRA7XX_CM_CLKMODE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c) -#define DRA7XX_CM_IDLEST_DPLL_PER_OFFSET 0x0040 -#define DRA7XX_CM_IDLEST_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040) -#define DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0044 -#define DRA7XX_CM_AUTOIDLE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044) -#define DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET 0x0048 -#define DRA7XX_CM_CLKSEL_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048) -#define DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET 0x004c -#define DRA7XX_CM_DIV_M2_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c) -#define DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0050 -#define DRA7XX_CM_DIV_M3_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050) -#define DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0054 -#define DRA7XX_CM_DIV_H11_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054) -#define DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET 0x0058 -#define DRA7XX_CM_DIV_H12_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058) -#define DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET 0x005c -#define DRA7XX_CM_DIV_H13_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c) -#define DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0060 -#define DRA7XX_CM_DIV_H14_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060) -#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0064 -#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0068 -#define DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET 0x007c -#define DRA7XX_CM_CLKMODE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c) -#define DRA7XX_CM_IDLEST_DPLL_USB_OFFSET 0x0080 -#define DRA7XX_CM_IDLEST_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080) -#define DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0084 -#define DRA7XX_CM_AUTOIDLE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084) -#define DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET 0x0088 -#define DRA7XX_CM_CLKSEL_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088) -#define DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET 0x008c -#define DRA7XX_CM_DIV_M2_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c) -#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a4 -#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00a8 -#define DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b0 -#define DRA7XX_CM_CLKDCOLDO_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0) -#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET 0x00fc -#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc) -#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET 0x0100 -#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100) -#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET 0x0104 -#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104) -#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET 0x0108 -#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108) -#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET 0x010c -#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c) -#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET 0x0110 -#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET 0x0114 -#define DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET 0x0118 -#define DRA7XX_CM_CLKMODE_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118) -#define DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET 0x011c -#define DRA7XX_CM_IDLEST_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c) -#define DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET 0x0120 -#define DRA7XX_CM_DIV_M2_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120) -#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET 0x0124 -#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124) - -/* CM_CORE.COREAON_CM_CORE register offsets */ -#define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028 -#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028) -#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038 -#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038) -#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET 0x0040 -#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040) -#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050 -#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050) -#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET 0x0058 -#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058) -#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET 0x0068 -#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068) -#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET 0x0078 -#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078) -#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET 0x0088 -#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088) -#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET 0x0098 -#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098) -#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET 0x00a0 -#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0) -#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET 0x00b0 -#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0) -#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET 0x00c0 -#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0) -#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET 0x00d0 -#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0) - -/* CM_CORE.CORE_CM_CORE register offsets */ -#define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008 -#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020 -#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020) -#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET 0x0028 -#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028) -#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET 0x0030 -#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030) -#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET 0x0050 -#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050) -#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET 0x0058 -#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058) -#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET 0x0060 -#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060) -#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET 0x0068 -#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068) -#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET 0x0070 -#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070) -#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET 0x0078 -#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078) -#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET 0x0080 -#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080) -#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET 0x0088 -#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088) -#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET 0x0090 -#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090) -#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET 0x0098 -#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098) -#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET 0x00a0 -#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0) -#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET 0x00a8 -#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8) -#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET 0x00b0 -#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0) -#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET 0x00b8 -#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8) -#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET 0x00c0 -#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0) -#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET 0x00c8 -#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8) -#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET 0x00d0 -#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0) -#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET 0x00d8 -#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8) -#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET 0x00f0 -#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0) -#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET 0x00f8 -#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8) -#define DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET 0x0200 -#define DRA7XX_CM_IPU2_STATICDEP_OFFSET 0x0204 -#define DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET 0x0208 -#define DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET 0x0220 -#define DRA7XX_CM_IPU2_IPU2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220) -#define DRA7XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300 -#define DRA7XX_CM_DMA_STATICDEP_OFFSET 0x0304 -#define DRA7XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308 -#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320 -#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320) -#define DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400 -#define DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420 -#define DRA7XX_CM_EMIF_DMM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420) -#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428 -#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428) -#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430 -#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430) -#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438 -#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438) -#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440 -#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440) -#define DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET 0x0500 -#define DRA7XX_CM_ATL_ATL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500) -#define DRA7XX_CM_ATL_CLKSTCTRL_OFFSET 0x0520 -#define DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600 -#define DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608 -#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620 -#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620) -#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628 -#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628) -#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET 0x0630 -#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630) -#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638 -#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638) -#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640 -#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640) -#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET 0x0648 -#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648) -#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET 0x0650 -#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650) -#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET 0x0658 -#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658) -#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET 0x0660 -#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660) -#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET 0x0668 -#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668) -#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET 0x0670 -#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670) -#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET 0x0678 -#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678) -#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET 0x0680 -#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680) -#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET 0x0688 -#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688) -#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET 0x0690 -#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690) -#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET 0x0698 -#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698) -#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET 0x06a0 -#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0) -#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET 0x06a8 -#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8) -#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET 0x06b0 -#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0) -#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET 0x06b8 -#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8) -#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET 0x06c0 -#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0) -#define DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700 -#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET 0x0720 -#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720) -#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728 -#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728) -#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740 -#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740) -#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748 -#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748) -#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750 -#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750) - -/* CM_CORE.IVA_CM_CORE register offsets */ -#define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_IVA_STATICDEP_OFFSET 0x0004 -#define DRA7XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008 -#define DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020 -#define DRA7XX_CM_IVA_IVA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020) -#define DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028 -#define DRA7XX_CM_IVA_SL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028) - -/* CM_CORE.CAM_CM_CORE register offsets */ -#define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_CAM_STATICDEP_OFFSET 0x0004 -#define DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET 0x0020 -#define DRA7XX_CM_CAM_VIP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020) -#define DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET 0x0028 -#define DRA7XX_CM_CAM_VIP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028) -#define DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET 0x0030 -#define DRA7XX_CM_CAM_VIP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030) -#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET 0x0038 -#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038) -#define DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET 0x0040 -#define DRA7XX_CM_CAM_CSI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040) -#define DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET 0x0048 -#define DRA7XX_CM_CAM_CSI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048) - -/* CM_CORE.DSS_CM_CORE register offsets */ -#define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_DSS_STATICDEP_OFFSET 0x0004 -#define DRA7XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008 -#define DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020 -#define DRA7XX_CM_DSS_DSS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020) -#define DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030 -#define DRA7XX_CM_DSS_BB2D_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030) -#define DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET 0x003c -#define DRA7XX_CM_DSS_SDVENC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c) - -/* CM_CORE.GPU_CM_CORE register offsets */ -#define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_GPU_STATICDEP_OFFSET 0x0004 -#define DRA7XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008 -#define DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020 -#define DRA7XX_CM_GPU_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020) - -/* CM_CORE.L3INIT_CM_CORE register offsets */ -#define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_L3INIT_STATICDEP_OFFSET 0x0004 -#define DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008 -#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028 -#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028) -#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030 -#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030) -#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET 0x0040 -#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040) -#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET 0x0048 -#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048) -#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET 0x0050 -#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050) -#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET 0x0058 -#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058) -#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078 -#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078) -#define DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088 -#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088) -#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0 -#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4 -#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET 0x00b0 -#define DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b0) -#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET 0x00b8 -#define DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00b8) -#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0 -#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4 -#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8 -#define DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET 0x00d0 -#define DRA7XX_CM_GMAC_GMAC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0) -#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0 -#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0) -#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8 -#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8) -#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET 0x00f0 -#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0) - -/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */ -#define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020 -#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020) - -/* CM_CORE.L4PER_CM_CORE register offsets */ -#define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0008 -#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET 0x000c -#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c) -#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET 0x0014 -#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014) -#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET 0x0018 -#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018) -#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET 0x0020 -#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020) -#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0028 -#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028) -#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0030 -#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030) -#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0038 -#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038) -#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0040 -#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040) -#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0048 -#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048) -#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0050 -#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050) -#define DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058 -#define DRA7XX_CM_L4PER_ELM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058) -#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060 -#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060) -#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068 -#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068) -#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070 -#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070) -#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078 -#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078) -#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080 -#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080) -#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088 -#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088) -#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET 0x0090 -#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090) -#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET 0x0098 -#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098) -#define DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0 -#define DRA7XX_CM_L4PER_I2C1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0) -#define DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8 -#define DRA7XX_CM_L4PER_I2C2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8) -#define DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0 -#define DRA7XX_CM_L4PER_I2C3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0) -#define DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8 -#define DRA7XX_CM_L4PER_I2C4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8) -#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET 0x00c0 -#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0) -#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET 0x00c4 -#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4) -#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET 0x00c8 -#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8) -#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET 0x00d0 -#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0) -#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET 0x00d8 -#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8) -#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0 -#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0) -#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8 -#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8) -#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100 -#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100) -#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108 -#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108) -#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0110 -#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110) -#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0118 -#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118) -#define DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0120 -#define DRA7XX_CM_L4PER_MMC3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120) -#define DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0128 -#define DRA7XX_CM_L4PER_MMC4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128) -#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET 0x0130 -#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130) -#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET 0x0138 -#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138) -#define DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140 -#define DRA7XX_CM_L4PER_UART1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140) -#define DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148 -#define DRA7XX_CM_L4PER_UART2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148) -#define DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150 -#define DRA7XX_CM_L4PER_UART3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150) -#define DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158 -#define DRA7XX_CM_L4PER_UART4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158) -#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET 0x0160 -#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160) -#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET 0x0168 -#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168) -#define DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0170 -#define DRA7XX_CM_L4PER_UART5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170) -#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET 0x0178 -#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178) -#define DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180 -#define DRA7XX_CM_L4SEC_STATICDEP_OFFSET 0x0184 -#define DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188 -#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET 0x0190 -#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190) -#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET 0x0198 -#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198) -#define DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0 -#define DRA7XX_CM_L4SEC_AES1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0) -#define DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8 -#define DRA7XX_CM_L4SEC_AES2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8) -#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0 -#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0) -#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x01b8 -#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8) -#define DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0 -#define DRA7XX_CM_L4SEC_RNG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0) -#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8 -#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8) -#define DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET 0x01d0 -#define DRA7XX_CM_L4PER2_UART7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0) -#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x01d8 -#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8) -#define DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET 0x01e0 -#define DRA7XX_CM_L4PER2_UART8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0) -#define DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET 0x01e8 -#define DRA7XX_CM_L4PER2_UART9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8) -#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET 0x01f0 -#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0) -#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET 0x01f8 -#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8) -#define DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET 0x01fc -#define DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET 0x0200 -#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET 0x0204 -#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204) -#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET 0x0208 -#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208) -#define DRA7XX_CM_L4PER2_STATICDEP_OFFSET 0x020c -#define DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET 0x0210 -#define DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET 0x0214 - #endif diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h index 63b362bfc4d9..af63d1892c33 100644 --- a/arch/arm/mach-omap2/cm33xx.h +++ b/arch/arm/mach-omap2/cm33xx.h @@ -37,8 +37,6 @@ #define AM33XX_CM_GFX_MOD 0x0900 #define AM33XX_CM_CEFUSE_MOD 0x0A00 -/* CM */ - /* CM.PER_CM register offsets */ #define AM33XX_CM_PER_L4LS_CLKSTCTRL_OFFSET 0x0000 #define AM33XX_CM_PER_L4LS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0000) @@ -48,330 +46,52 @@ #define AM33XX_CM_PER_L4FW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0008) #define AM33XX_CM_PER_L3_CLKSTCTRL_OFFSET 0x000c #define AM33XX_CM_PER_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x000c) -#define AM33XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0014 -#define AM33XX_CM_PER_CPGMAC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0014) -#define AM33XX_CM_PER_LCDC_CLKCTRL_OFFSET 0x0018 -#define AM33XX_CM_PER_LCDC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0018) -#define AM33XX_CM_PER_USB0_CLKCTRL_OFFSET 0x001c -#define AM33XX_CM_PER_USB0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x001c) -#define AM33XX_CM_PER_MLB_CLKCTRL_OFFSET 0x0020 -#define AM33XX_CM_PER_MLB_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0020) -#define AM33XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0024 -#define AM33XX_CM_PER_TPTC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0024) #define AM33XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0028 #define AM33XX_CM_PER_EMIF_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0028) -#define AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x002c -#define AM33XX_CM_PER_OCMCRAM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x002c) -#define AM33XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0030 -#define AM33XX_CM_PER_GPMC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0030) -#define AM33XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0034 -#define AM33XX_CM_PER_MCASP0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0034) -#define AM33XX_CM_PER_UART5_CLKCTRL_OFFSET 0x0038 -#define AM33XX_CM_PER_UART5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0038) -#define AM33XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x003c -#define AM33XX_CM_PER_MMC0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x003c) -#define AM33XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0040 -#define AM33XX_CM_PER_ELM_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0040) -#define AM33XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x0044 -#define AM33XX_CM_PER_I2C2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0044) -#define AM33XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x0048 -#define AM33XX_CM_PER_I2C1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0048) -#define AM33XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x004c -#define AM33XX_CM_PER_SPI0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x004c) -#define AM33XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0050 -#define AM33XX_CM_PER_SPI1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0050) -#define AM33XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0054 -#define AM33XX_CM_PER_SPI2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0054) -#define AM33XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0058 -#define AM33XX_CM_PER_SPI3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0058) -#define AM33XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0060 -#define AM33XX_CM_PER_L4LS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0060) -#define AM33XX_CM_PER_L4FW_CLKCTRL_OFFSET 0x0064 -#define AM33XX_CM_PER_L4FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0064) -#define AM33XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0068 -#define AM33XX_CM_PER_MCASP1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0068) -#define AM33XX_CM_PER_UART1_CLKCTRL_OFFSET 0x006c -#define AM33XX_CM_PER_UART1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x006c) -#define AM33XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0070 -#define AM33XX_CM_PER_UART2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0070) -#define AM33XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0074 -#define AM33XX_CM_PER_UART3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0074) -#define AM33XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0078 -#define AM33XX_CM_PER_UART4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0078) -#define AM33XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x007c -#define AM33XX_CM_PER_TIMER7_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x007c) -#define AM33XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0080 -#define AM33XX_CM_PER_TIMER2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0080) -#define AM33XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0084 -#define AM33XX_CM_PER_TIMER3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0084) -#define AM33XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0088 -#define AM33XX_CM_PER_TIMER4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0088) -#define AM33XX_CM_PER_MCASP2_CLKCTRL_OFFSET 0x008c -#define AM33XX_CM_PER_MCASP2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x008c) -#define AM33XX_CM_PER_RNG_CLKCTRL_OFFSET 0x0090 -#define AM33XX_CM_PER_RNG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0090) -#define AM33XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0094 -#define AM33XX_CM_PER_AES0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0094) -#define AM33XX_CM_PER_AES1_CLKCTRL_OFFSET 0x0098 -#define AM33XX_CM_PER_AES1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0098) -#define AM33XX_CM_PER_DES_CLKCTRL_OFFSET 0x009c -#define AM33XX_CM_PER_DES_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x009c) -#define AM33XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x00a0 -#define AM33XX_CM_PER_SHA0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a0) -#define AM33XX_CM_PER_PKA_CLKCTRL_OFFSET 0x00a4 -#define AM33XX_CM_PER_PKA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a4) -#define AM33XX_CM_PER_GPIO6_CLKCTRL_OFFSET 0x00a8 -#define AM33XX_CM_PER_GPIO6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00a8) -#define AM33XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x00ac -#define AM33XX_CM_PER_GPIO1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ac) -#define AM33XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x00b0 -#define AM33XX_CM_PER_GPIO2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b0) -#define AM33XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x00b4 -#define AM33XX_CM_PER_GPIO3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b4) -#define AM33XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x00b8 -#define AM33XX_CM_PER_GPIO4_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00b8) -#define AM33XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x00bc -#define AM33XX_CM_PER_TPCC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00bc) -#define AM33XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x00c0 -#define AM33XX_CM_PER_DCAN0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c0) -#define AM33XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x00c4 -#define AM33XX_CM_PER_DCAN1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00c4) -#define AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x00cc -#define AM33XX_CM_PER_EPWMSS1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00cc) -#define AM33XX_CM_PER_EMIF_FW_CLKCTRL_OFFSET 0x00d0 -#define AM33XX_CM_PER_EMIF_FW_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d0) -#define AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x00d4 -#define AM33XX_CM_PER_EPWMSS0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d4) -#define AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x00d8 -#define AM33XX_CM_PER_EPWMSS2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00d8) -#define AM33XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x00dc -#define AM33XX_CM_PER_L3_INSTR_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00dc) -#define AM33XX_CM_PER_L3_CLKCTRL_OFFSET 0x00e0 -#define AM33XX_CM_PER_L3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e0) -#define AM33XX_CM_PER_IEEE5000_CLKCTRL_OFFSET 0x00e4 -#define AM33XX_CM_PER_IEEE5000_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e4) -#define AM33XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x00e8 -#define AM33XX_CM_PER_PRUSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00e8) -#define AM33XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x00ec -#define AM33XX_CM_PER_TIMER5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00ec) -#define AM33XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x00f0 -#define AM33XX_CM_PER_TIMER6_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f0) -#define AM33XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x00f4 -#define AM33XX_CM_PER_MMC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f4) -#define AM33XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x00f8 -#define AM33XX_CM_PER_MMC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00f8) -#define AM33XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x00fc -#define AM33XX_CM_PER_TPTC1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x00fc) -#define AM33XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0100 -#define AM33XX_CM_PER_TPTC2_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0100) -#define AM33XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0104 -#define AM33XX_CM_PER_GPIO5_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0104) -#define AM33XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x010c -#define AM33XX_CM_PER_SPINLOCK_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x010c) -#define AM33XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x0110 -#define AM33XX_CM_PER_MAILBOX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0110) #define AM33XX_CM_PER_L4HS_CLKSTCTRL_OFFSET 0x011c #define AM33XX_CM_PER_L4HS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x011c) -#define AM33XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x0120 -#define AM33XX_CM_PER_L4HS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0120) -#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL_OFFSET 0x0124 -#define AM33XX_CM_PER_MSTR_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0124) -#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL_OFFSET 0x0128 -#define AM33XX_CM_PER_SLV_EXPS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0128) #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL_OFFSET 0x012c #define AM33XX_CM_PER_OCPWP_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x012c) -#define AM33XX_CM_PER_OCPWP_CLKCTRL_OFFSET 0x0130 -#define AM33XX_CM_PER_OCPWP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0130) -#define AM33XX_CM_PER_MAILBOX1_CLKCTRL_OFFSET 0x0134 -#define AM33XX_CM_PER_MAILBOX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0134) #define AM33XX_CM_PER_PRUSS_CLKSTCTRL_OFFSET 0x0140 #define AM33XX_CM_PER_PRUSS_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0140) #define AM33XX_CM_PER_CPSW_CLKSTCTRL_OFFSET 0x0144 #define AM33XX_CM_PER_CPSW_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0144) #define AM33XX_CM_PER_LCDC_CLKSTCTRL_OFFSET 0x0148 #define AM33XX_CM_PER_LCDC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0148) -#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL_OFFSET 0x014c -#define AM33XX_CM_PER_CLKDIV32K_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x014c) #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL_OFFSET 0x0150 #define AM33XX_CM_PER_CLK_24MHZ_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_PER_MOD, 0x0150) /* CM.WKUP_CM register offsets */ #define AM33XX_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 #define AM33XX_CM_WKUP_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0000) -#define AM33XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0004 -#define AM33XX_CM_WKUP_CONTROL_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0004) -#define AM33XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0008 -#define AM33XX_CM_WKUP_GPIO0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0008) -#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x000c -#define AM33XX_CM_WKUP_L4WKUP_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x000c) -#define AM33XX_CM_WKUP_TIMER0_CLKCTRL_OFFSET 0x0010 -#define AM33XX_CM_WKUP_TIMER0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0010) -#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET 0x0014 -#define AM33XX_CM_WKUP_DEBUGSS_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0014) #define AM33XX_CM_L3_AON_CLKSTCTRL_OFFSET 0x0018 #define AM33XX_CM_L3_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0018) -#define AM33XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x001c -#define AM33XX_CM_AUTOIDLE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x001c) -#define AM33XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0020 -#define AM33XX_CM_IDLEST_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0020) -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0024 -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0024) -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x0028 -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0028) -#define AM33XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x002c -#define AM33XX_CM_CLKSEL_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x002c) -#define AM33XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0030 -#define AM33XX_CM_AUTOIDLE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0030) -#define AM33XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0034 -#define AM33XX_CM_IDLEST_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0034) -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x0038 -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0038) -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x003c -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x003c) -#define AM33XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x0040 -#define AM33XX_CM_CLKSEL_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0040) -#define AM33XX_CM_AUTOIDLE_DPLL_DISP_OFFSET 0x0044 -#define AM33XX_CM_AUTOIDLE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0044) -#define AM33XX_CM_IDLEST_DPLL_DISP_OFFSET 0x0048 -#define AM33XX_CM_IDLEST_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0048) -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP_OFFSET 0x004c -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x004c) -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP_OFFSET 0x0050 -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0050) -#define AM33XX_CM_CLKSEL_DPLL_DISP_OFFSET 0x0054 -#define AM33XX_CM_CLKSEL_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0054) -#define AM33XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0058 -#define AM33XX_CM_AUTOIDLE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0058) -#define AM33XX_CM_IDLEST_DPLL_CORE_OFFSET 0x005c -#define AM33XX_CM_IDLEST_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x005c) -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0060 -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0060) -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x0064 -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0064) -#define AM33XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x0068 -#define AM33XX_CM_CLKSEL_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0068) -#define AM33XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x006c -#define AM33XX_CM_AUTOIDLE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x006c) -#define AM33XX_CM_IDLEST_DPLL_PER_OFFSET 0x0070 -#define AM33XX_CM_IDLEST_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0070) -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0074 -#define AM33XX_CM_SSC_DELTAMSTEP_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0074) -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0078 -#define AM33XX_CM_SSC_MODFREQDIV_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0078) -#define AM33XX_CM_CLKDCOLDO_DPLL_PER_OFFSET 0x007c -#define AM33XX_CM_CLKDCOLDO_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x007c) -#define AM33XX_CM_DIV_M4_DPLL_CORE_OFFSET 0x0080 -#define AM33XX_CM_DIV_M4_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0080) -#define AM33XX_CM_DIV_M5_DPLL_CORE_OFFSET 0x0084 -#define AM33XX_CM_DIV_M5_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0084) -#define AM33XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0088 -#define AM33XX_CM_CLKMODE_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0088) -#define AM33XX_CM_CLKMODE_DPLL_PER_OFFSET 0x008c -#define AM33XX_CM_CLKMODE_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x008c) -#define AM33XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0090 -#define AM33XX_CM_CLKMODE_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0090) -#define AM33XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0094 -#define AM33XX_CM_CLKMODE_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0094) -#define AM33XX_CM_CLKMODE_DPLL_DISP_OFFSET 0x0098 -#define AM33XX_CM_CLKMODE_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x0098) -#define AM33XX_CM_CLKSEL_DPLL_PERIPH_OFFSET 0x009c -#define AM33XX_CM_CLKSEL_DPLL_PERIPH AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x009c) -#define AM33XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x00a0 -#define AM33XX_CM_DIV_M2_DPLL_DDR AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a0) -#define AM33XX_CM_DIV_M2_DPLL_DISP_OFFSET 0x00a4 -#define AM33XX_CM_DIV_M2_DPLL_DISP AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a4) -#define AM33XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x00a8 -#define AM33XX_CM_DIV_M2_DPLL_MPU AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00a8) -#define AM33XX_CM_DIV_M2_DPLL_PER_OFFSET 0x00ac -#define AM33XX_CM_DIV_M2_DPLL_PER AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00ac) -#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x00b0 -#define AM33XX_CM_WKUP_WKUP_M3_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b0) -#define AM33XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x00b4 -#define AM33XX_CM_WKUP_UART0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b4) -#define AM33XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x00b8 -#define AM33XX_CM_WKUP_I2C0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00b8) -#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x00bc -#define AM33XX_CM_WKUP_ADC_TSC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00bc) -#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x00c0 -#define AM33XX_CM_WKUP_SMARTREFLEX0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c0) -#define AM33XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x00c4 -#define AM33XX_CM_WKUP_TIMER1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c4) -#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x00c8 -#define AM33XX_CM_WKUP_SMARTREFLEX1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00c8) #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL_OFFSET 0x00cc #define AM33XX_CM_L4_WKUP_AON_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00cc) -#define AM33XX_CM_WKUP_WDT0_CLKCTRL_OFFSET 0x00d0 -#define AM33XX_CM_WKUP_WDT0_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d0) -#define AM33XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x00d4 -#define AM33XX_CM_WKUP_WDT1_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d4) -#define AM33XX_CM_DIV_M6_DPLL_CORE_OFFSET 0x00d8 -#define AM33XX_CM_DIV_M6_DPLL_CORE AM33XX_CM_REGADDR(AM33XX_CM_WKUP_MOD, 0x00d8) /* CM.DPLL_CM register offsets */ -#define AM33XX_CLKSEL_TIMER7_CLK_OFFSET 0x0004 -#define AM33XX_CLKSEL_TIMER7_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0004) -#define AM33XX_CLKSEL_TIMER2_CLK_OFFSET 0x0008 -#define AM33XX_CLKSEL_TIMER2_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0008) -#define AM33XX_CLKSEL_TIMER3_CLK_OFFSET 0x000c -#define AM33XX_CLKSEL_TIMER3_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x000c) -#define AM33XX_CLKSEL_TIMER4_CLK_OFFSET 0x0010 -#define AM33XX_CLKSEL_TIMER4_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0010) -#define AM33XX_CM_MAC_CLKSEL_OFFSET 0x0014 -#define AM33XX_CM_MAC_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0014) -#define AM33XX_CLKSEL_TIMER5_CLK_OFFSET 0x0018 -#define AM33XX_CLKSEL_TIMER5_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0018) -#define AM33XX_CLKSEL_TIMER6_CLK_OFFSET 0x001c -#define AM33XX_CLKSEL_TIMER6_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x001c) -#define AM33XX_CM_CPTS_RFT_CLKSEL_OFFSET 0x0020 -#define AM33XX_CM_CPTS_RFT_CLKSEL AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0020) -#define AM33XX_CLKSEL_TIMER1MS_CLK_OFFSET 0x0028 -#define AM33XX_CLKSEL_TIMER1MS_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0028) -#define AM33XX_CLKSEL_GFX_FCLK_OFFSET 0x002c #define AM33XX_CLKSEL_GFX_FCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x002c) -#define AM33XX_CLKSEL_PRUSS_OCP_CLK_OFFSET 0x0030 -#define AM33XX_CLKSEL_PRUSS_OCP_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0030) -#define AM33XX_CLKSEL_LCDC_PIXEL_CLK_OFFSET 0x0034 -#define AM33XX_CLKSEL_LCDC_PIXEL_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0034) -#define AM33XX_CLKSEL_WDT1_CLK_OFFSET 0x0038 -#define AM33XX_CLKSEL_WDT1_CLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x0038) -#define AM33XX_CLKSEL_GPIO0_DBCLK_OFFSET 0x003c -#define AM33XX_CLKSEL_GPIO0_DBCLK AM33XX_CM_REGADDR(AM33XX_CM_DPLL_MOD, 0x003c) /* CM.MPU_CM register offsets */ #define AM33XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000 #define AM33XX_CM_MPU_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0000) -#define AM33XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0004 #define AM33XX_CM_MPU_MPU_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_MPU_MOD, 0x0004) /* CM.DEVICE_CM register offsets */ -#define AM33XX_CM_CLKOUT_CTRL_OFFSET 0x0000 -#define AM33XX_CM_CLKOUT_CTRL AM33XX_CM_REGADDR(AM33XX_CM_DEVICE_MOD, 0x0000) /* CM.RTC_CM register offsets */ -#define AM33XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0000 -#define AM33XX_CM_RTC_RTC_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0000) #define AM33XX_CM_RTC_CLKSTCTRL_OFFSET 0x0004 #define AM33XX_CM_RTC_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_RTC_MOD, 0x0004) /* CM.GFX_CM register offsets */ #define AM33XX_CM_GFX_L3_CLKSTCTRL_OFFSET 0x0000 #define AM33XX_CM_GFX_L3_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0000) -#define AM33XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0004 -#define AM33XX_CM_GFX_GFX_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0004) -#define AM33XX_CM_GFX_BITBLT_CLKCTRL_OFFSET 0x0008 -#define AM33XX_CM_GFX_BITBLT_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0008) #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1_OFFSET 0x000c #define AM33XX_CM_GFX_L4LS_GFX_CLKSTCTRL__1 AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x000c) -#define AM33XX_CM_GFX_MMUCFG_CLKCTRL_OFFSET 0x0010 -#define AM33XX_CM_GFX_MMUCFG_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0010) -#define AM33XX_CM_GFX_MMUDATA_CLKCTRL_OFFSET 0x0014 -#define AM33XX_CM_GFX_MMUDATA_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_GFX_MOD, 0x0014) /* CM.CEFUSE_CM register offsets */ #define AM33XX_CM_CEFUSE_CLKSTCTRL_OFFSET 0x0000 #define AM33XX_CM_CEFUSE_CLKSTCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0000) -#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020 -#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020) #ifndef __ASSEMBLER__ diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 0c2936c7a379..ccb0e3732c0d 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -812,7 +812,7 @@ static struct clk *_lookup_clkctrl_clk(struct omap_hwmod *oh) } /** - * _init_main_clk - get a struct clk * for the the hwmod's main functional clk + * _init_main_clk - get a struct clk * for the hwmod's main functional clk * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh _clk (main @@ -862,7 +862,7 @@ static int _init_main_clk(struct omap_hwmod *oh) } /** - * _init_interface_clks - get a struct clk * for the the hwmod's interface clks + * _init_interface_clks - get a struct clk * for the hwmod's interface clks * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh OCP slave interface @@ -901,7 +901,7 @@ static int _init_interface_clks(struct omap_hwmod *oh) } /** - * _init_opt_clk - get a struct clk * for the the hwmod's optional clocks + * _init_opt_clk - get a struct clk * for the hwmod's optional clocks * @oh: struct omap_hwmod * * * Called from _init_clocks(). Populates the @oh omap_hwmod_opt_clk diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c index 765809b214e7..e7fd29a502a0 100644 --- a/arch/arm/mach-omap2/pdata-quirks.c +++ b/arch/arm/mach-omap2/pdata-quirks.c @@ -274,34 +274,10 @@ static void __init omap3_pandora_legacy_init(void) } #endif /* CONFIG_ARCH_OMAP3 */ -#ifdef CONFIG_SOC_OMAP5 -static void __init omap5_uevm_legacy_init(void) -{ -} -#endif - #ifdef CONFIG_SOC_DRA7XX static struct iommu_platform_data dra7_ipu1_dsp_iommu_pdata = { .set_pwrdm_constraint = omap_iommu_set_pwrdm_constraint, }; - -static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1; -static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2; -static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3; - -static void __init dra7x_evm_mmc_quirk(void) -{ - if (omap_rev() == DRA752_REV_ES1_1 || omap_rev() == DRA752_REV_ES1_0) { - dra7_hsmmc_data_mmc1.version = "rev11"; - dra7_hsmmc_data_mmc1.max_freq = 96000000; - - dra7_hsmmc_data_mmc2.version = "rev11"; - dra7_hsmmc_data_mmc2.max_freq = 48000000; - - dra7_hsmmc_data_mmc3.version = "rev11"; - dra7_hsmmc_data_mmc3.max_freq = 48000000; - } -} #endif static struct clockdomain *ti_sysc_find_one_clockdomain(struct clk *clk) @@ -508,12 +484,6 @@ static struct of_dev_auxdata omap_auxdata_lookup[] = { "4a0d9000.smartreflex", &omap_sr_pdata[OMAP_SR_MPU]), #endif #ifdef CONFIG_SOC_DRA7XX - OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x4809c000, "4809c000.mmc", - &dra7_hsmmc_data_mmc1), - OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480b4000, "480b4000.mmc", - &dra7_hsmmc_data_mmc2), - OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc", - &dra7_hsmmc_data_mmc3), OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x40d01000, "40d01000.mmu", &dra7_ipu1_dsp_iommu_pdata), OF_DEV_AUXDATA("ti,dra7-dsp-iommu", 0x41501000, "41501000.mmu", @@ -549,12 +519,6 @@ static struct pdata_init pdata_quirks[] __initdata = { { "openpandora,omap3-pandora-600mhz", omap3_pandora_legacy_init, }, { "openpandora,omap3-pandora-1ghz", omap3_pandora_legacy_init, }, #endif -#ifdef CONFIG_SOC_OMAP5 - { "ti,omap5-uevm", omap5_uevm_legacy_init, }, -#endif -#ifdef CONFIG_SOC_DRA7XX - { "ti,dra7-evm", dra7x_evm_mmc_quirk, }, -#endif { /* sentinel */ }, }; diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 0a5b87e2a4b0..2d747f6cffe8 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -626,7 +626,7 @@ int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) * powerdomain @pwrdm will enter when the powerdomain enters retention. * This will be either RETENTION or OFF, if supported. Returns * -EINVAL if the powerdomain pointer is null or the target power - * state is not not supported, or returns 0 upon success. + * state is not supported, or returns 0 upon success. */ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) { @@ -658,7 +658,7 @@ int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) * state. @bank will be a number from 0 to 3, and represents different * types of memory, depending on the powerdomain. Returns -EINVAL if * the powerdomain pointer is null or the target power state is not - * not supported for this memory bank, -EEXIST if the target memory + * supported for this memory bank, -EEXIST if the target memory * bank does not exist or is not controllable, or returns 0 upon * success. */ @@ -696,7 +696,7 @@ int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst) * different types of memory, depending on the powerdomain. @pwrst * will be either RETENTION or OFF, if supported. Returns -EINVAL if * the powerdomain pointer is null or the target power state is not - * not supported for this memory bank, -EEXIST if the target memory + * supported for this memory bank, -EEXIST if the target memory * bank does not exist or is not controllable, or returns 0 upon * success. */ diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h index 899da0ae9800..b65cccab6ad9 100644 --- a/arch/arm/mach-omap2/prcm43xx.h +++ b/arch/arm/mach-omap2/prcm43xx.h @@ -32,20 +32,8 @@ /* Other PRM offsets */ #define AM43XX_PRM_IO_PMCTRL_OFFSET 0x0024 -/* RM RSTCTRL offsets */ -#define AM43XX_RM_PER_RSTCTRL_OFFSET 0x0010 -#define AM43XX_RM_GFX_RSTCTRL_OFFSET 0x0010 -#define AM43XX_RM_WKUP_RSTCTRL_OFFSET 0x0010 - -/* RM RSTST offsets */ -#define AM43XX_RM_GFX_RSTST_OFFSET 0x0014 -#define AM43XX_RM_PER_RSTST_OFFSET 0x0014 -#define AM43XX_RM_WKUP_RSTST_OFFSET 0x0014 - /* CM instances */ #define AM43XX_CM_WKUP_INST 0x2800 -#define AM43XX_CM_DEVICE_INST 0x4100 -#define AM43XX_CM_DPLL_INST 0x4200 #define AM43XX_CM_MPU_INST 0x8300 #define AM43XX_CM_GFX_INST 0x8400 #define AM43XX_CM_RTC_INST 0x8500 @@ -74,89 +62,7 @@ #define AM43XX_CM_PER_OCPWP_L3_CDOFFS 0x0c00 /* CLK CTRL offsets */ -#define AM43XX_CM_PER_UART1_CLKCTRL_OFFSET 0x0580 -#define AM43XX_CM_PER_UART2_CLKCTRL_OFFSET 0x0588 -#define AM43XX_CM_PER_UART3_CLKCTRL_OFFSET 0x0590 -#define AM43XX_CM_PER_UART4_CLKCTRL_OFFSET 0x0598 -#define AM43XX_CM_PER_UART5_CLKCTRL_OFFSET 0x05a0 -#define AM43XX_CM_PER_DCAN0_CLKCTRL_OFFSET 0x0428 -#define AM43XX_CM_PER_DCAN1_CLKCTRL_OFFSET 0x0430 -#define AM43XX_CM_PER_ELM_CLKCTRL_OFFSET 0x0468 -#define AM43XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET 0x0438 -#define AM43XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET 0x0440 -#define AM43XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET 0x0448 -#define AM43XX_CM_PER_GPIO1_CLKCTRL_OFFSET 0x0478 -#define AM43XX_CM_PER_GPIO2_CLKCTRL_OFFSET 0x0480 -#define AM43XX_CM_PER_GPIO3_CLKCTRL_OFFSET 0x0488 -#define AM43XX_CM_PER_I2C1_CLKCTRL_OFFSET 0x04a8 -#define AM43XX_CM_PER_I2C2_CLKCTRL_OFFSET 0x04b0 -#define AM43XX_CM_PER_MAILBOX0_CLKCTRL_OFFSET 0x04b8 -#define AM43XX_CM_PER_MMC0_CLKCTRL_OFFSET 0x04c0 -#define AM43XX_CM_PER_MMC1_CLKCTRL_OFFSET 0x04c8 -#define AM43XX_CM_PER_RNG_CLKCTRL_OFFSET 0x04e0 -#define AM43XX_CM_PER_SPI0_CLKCTRL_OFFSET 0x0500 -#define AM43XX_CM_PER_SPI1_CLKCTRL_OFFSET 0x0508 -#define AM43XX_CM_PER_SPINLOCK_CLKCTRL_OFFSET 0x0528 -#define AM43XX_CM_PER_TIMER2_CLKCTRL_OFFSET 0x0530 -#define AM43XX_CM_PER_TIMER3_CLKCTRL_OFFSET 0x0538 -#define AM43XX_CM_PER_TIMER4_CLKCTRL_OFFSET 0x0540 -#define AM43XX_CM_PER_TIMER5_CLKCTRL_OFFSET 0x0548 -#define AM43XX_CM_PER_TIMER6_CLKCTRL_OFFSET 0x0550 -#define AM43XX_CM_PER_TIMER7_CLKCTRL_OFFSET 0x0558 -#define AM43XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET 0x0228 -#define AM43XX_CM_WKUP_CONTROL_CLKCTRL_OFFSET 0x0360 -#define AM43XX_CM_WKUP_SMARTREFLEX0_CLKCTRL_OFFSET 0x0350 -#define AM43XX_CM_WKUP_SMARTREFLEX1_CLKCTRL_OFFSET 0x0358 -#define AM43XX_CM_WKUP_UART0_CLKCTRL_OFFSET 0x0348 -#define AM43XX_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0328 -#define AM43XX_CM_WKUP_I2C0_CLKCTRL_OFFSET 0x0340 -#define AM43XX_CM_WKUP_GPIO0_CLKCTRL_OFFSET 0x0368 -#define AM43XX_CM_WKUP_ADC_TSC_CLKCTRL_OFFSET 0x0120 -#define AM43XX_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0338 -#define AM43XX_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0220 -#define AM43XX_CM_RTC_RTC_CLKCTRL_OFFSET 0x0020 -#define AM43XX_CM_PER_MMC2_CLKCTRL_OFFSET 0x0248 -#define AM43XX_CM_PER_QSPI_CLKCTRL_OFFSET 0x0258 -#define AM43XX_CM_PER_GPMC_CLKCTRL_OFFSET 0x0220 -#define AM43XX_CM_PER_MCASP0_CLKCTRL_OFFSET 0x0238 -#define AM43XX_CM_PER_MCASP1_CLKCTRL_OFFSET 0x0240 -#define AM43XX_CM_PER_L4LS_CLKCTRL_OFFSET 0x0420 -#define AM43XX_CM_PER_L3_CLKCTRL_OFFSET 0x0020 -#define AM43XX_CM_PER_TPCC_CLKCTRL_OFFSET 0x0078 -#define AM43XX_CM_PER_TPTC0_CLKCTRL_OFFSET 0x0080 -#define AM43XX_CM_PER_TPTC1_CLKCTRL_OFFSET 0x0088 -#define AM43XX_CM_PER_TPTC2_CLKCTRL_OFFSET 0x0090 -#define AM43XX_CM_PER_CPGMAC0_CLKCTRL_OFFSET 0x0b20 -#define AM43XX_CM_PER_PRUSS_CLKCTRL_OFFSET 0x0320 -#define AM43XX_CM_GFX_GFX_CLKCTRL_OFFSET 0x0020 -#define AM43XX_CM_PER_L4HS_CLKCTRL_OFFSET 0x00a0 #define AM43XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020 -#define AM43XX_CM_PER_L3_INSTR_CLKCTRL_OFFSET 0x0040 -#define AM43XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET 0x0050 -#define AM43XX_CM_PER_SHA0_CLKCTRL_OFFSET 0x0058 -#define AM43XX_CM_PER_AES0_CLKCTRL_OFFSET 0x0028 -#define AM43XX_CM_PER_DES_CLKCTRL_OFFSET 0x0030 -#define AM43XX_CM_PER_TIMER8_CLKCTRL_OFFSET 0x0560 -#define AM43XX_CM_PER_TIMER9_CLKCTRL_OFFSET 0x0568 -#define AM43XX_CM_PER_TIMER10_CLKCTRL_OFFSET 0x0570 -#define AM43XX_CM_PER_TIMER11_CLKCTRL_OFFSET 0x0578 -#define AM43XX_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0230 -#define AM43XX_CM_PER_EPWMSS3_CLKCTRL_OFFSET 0x0450 -#define AM43XX_CM_PER_EPWMSS4_CLKCTRL_OFFSET 0x0458 -#define AM43XX_CM_PER_EPWMSS5_CLKCTRL_OFFSET 0x0460 -#define AM43XX_CM_PER_SPI2_CLKCTRL_OFFSET 0x0510 -#define AM43XX_CM_PER_SPI3_CLKCTRL_OFFSET 0x0518 -#define AM43XX_CM_PER_SPI4_CLKCTRL_OFFSET 0x0520 -#define AM43XX_CM_PER_GPIO4_CLKCTRL_OFFSET 0x0490 -#define AM43XX_CM_PER_GPIO5_CLKCTRL_OFFSET 0x0498 -#define AM43XX_CM_PER_USB_OTG_SS0_CLKCTRL_OFFSET 0x0260 -#define AM43XX_CM_PER_USBPHYOCP2SCP0_CLKCTRL_OFFSET 0x05B8 -#define AM43XX_CM_PER_USB_OTG_SS1_CLKCTRL_OFFSET 0x0268 -#define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0 -#define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20 -#define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET 0x04a0 -#define AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET 0x0068 -#define AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET 0x0070 #define AM43XX_CM_PER_EMIF_CLKCTRL_OFFSET 0x0720 #endif diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h index d0b7404565f1..a469a36c00d8 100644 --- a/arch/arm/mach-omap2/prm33xx.h +++ b/arch/arm/mach-omap2/prm33xx.h @@ -35,63 +35,27 @@ #define AM33XX_PRM_GFX_MOD 0x1100 #define AM33XX_PRM_CEFUSE_MOD 0x1200 -/* PRM */ - -/* PRM.OCP_SOCKET_PRM register offsets */ -#define AM33XX_REVISION_PRM_OFFSET 0x0000 -#define AM33XX_REVISION_PRM AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0000) -#define AM33XX_PRM_IRQSTATUS_MPU_OFFSET 0x0004 -#define AM33XX_PRM_IRQSTATUS_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0004) -#define AM33XX_PRM_IRQENABLE_MPU_OFFSET 0x0008 -#define AM33XX_PRM_IRQENABLE_MPU AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0008) -#define AM33XX_PRM_IRQSTATUS_M3_OFFSET 0x000c -#define AM33XX_PRM_IRQSTATUS_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x000c) -#define AM33XX_PRM_IRQENABLE_M3_OFFSET 0x0010 -#define AM33XX_PRM_IRQENABLE_M3 AM33XX_PRM_REGADDR(AM33XX_PRM_OCP_SOCKET_MOD, 0x0010) - /* PRM.PER_PRM register offsets */ -#define AM33XX_RM_PER_RSTCTRL_OFFSET 0x0000 -#define AM33XX_RM_PER_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0000) #define AM33XX_PM_PER_PWRSTST_OFFSET 0x0008 #define AM33XX_PM_PER_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x0008) #define AM33XX_PM_PER_PWRSTCTRL_OFFSET 0x000c #define AM33XX_PM_PER_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_PER_MOD, 0x000c) /* PRM.WKUP_PRM register offsets */ -#define AM33XX_RM_WKUP_RSTCTRL_OFFSET 0x0000 -#define AM33XX_RM_WKUP_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0000) #define AM33XX_PM_WKUP_PWRSTCTRL_OFFSET 0x0004 #define AM33XX_PM_WKUP_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0004) #define AM33XX_PM_WKUP_PWRSTST_OFFSET 0x0008 #define AM33XX_PM_WKUP_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x0008) -#define AM33XX_RM_WKUP_RSTST_OFFSET 0x000c -#define AM33XX_RM_WKUP_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_WKUP_MOD, 0x000c) /* PRM.MPU_PRM register offsets */ #define AM33XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 #define AM33XX_PM_MPU_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0000) #define AM33XX_PM_MPU_PWRSTST_OFFSET 0x0004 #define AM33XX_PM_MPU_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0004) -#define AM33XX_RM_MPU_RSTST_OFFSET 0x0008 -#define AM33XX_RM_MPU_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_MPU_MOD, 0x0008) /* PRM.DEVICE_PRM register offsets */ #define AM33XX_PRM_RSTCTRL_OFFSET 0x0000 #define AM33XX_PRM_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0000) -#define AM33XX_PRM_RSTTIME_OFFSET 0x0004 -#define AM33XX_PRM_RSTTIME AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0004) -#define AM33XX_PRM_RSTST_OFFSET 0x0008 -#define AM33XX_PRM_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0008) -#define AM33XX_PRM_SRAM_COUNT_OFFSET 0x000c -#define AM33XX_PRM_SRAM_COUNT AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x000c) -#define AM33XX_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x0010 -#define AM33XX_PRM_LDO_SRAM_CORE_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0010) -#define AM33XX_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x0014 -#define AM33XX_PRM_LDO_SRAM_CORE_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0014) -#define AM33XX_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x0018 -#define AM33XX_PRM_LDO_SRAM_MPU_SETUP AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x0018) -#define AM33XX_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x001c -#define AM33XX_PRM_LDO_SRAM_MPU_CTRL AM33XX_PRM_REGADDR(AM33XX_PRM_DEVICE_MOD, 0x001c) /* PRM.RTC_PRM register offsets */ #define AM33XX_PM_RTC_PWRSTCTRL_OFFSET 0x0000 @@ -102,12 +66,8 @@ /* PRM.GFX_PRM register offsets */ #define AM33XX_PM_GFX_PWRSTCTRL_OFFSET 0x0000 #define AM33XX_PM_GFX_PWRSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0000) -#define AM33XX_RM_GFX_RSTCTRL_OFFSET 0x0004 -#define AM33XX_RM_GFX_RSTCTRL AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0004) #define AM33XX_PM_GFX_PWRSTST_OFFSET 0x0010 #define AM33XX_PM_GFX_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0010) -#define AM33XX_RM_GFX_RSTST_OFFSET 0x0014 -#define AM33XX_RM_GFX_RSTST AM33XX_PRM_REGADDR(AM33XX_PRM_GFX_MOD, 0x0014) /* PRM.CEFUSE_PRM register offsets */ #define AM33XX_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index 1006d3c8c42e..fc7d4ed0bd9b 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -51,694 +51,64 @@ #define OMAP4430_PRM_EMU_INST 0x1900 #define OMAP4430_PRM_EMU_CM_INST 0x1a00 #define OMAP4430_PRM_DEVICE_INST 0x1b00 -#define OMAP4430_PRM_INSTR_INST 0x1f00 /* PRM clockdomain register offsets (from instance start) */ #define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000 #define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000 /* OMAP4 specific register offsets */ -#define OMAP4_RM_RSTCTRL 0x0000 #define OMAP4_RM_RSTST 0x0004 -#define OMAP4_RM_RSTTIME 0x0008 #define OMAP4_PM_PWSTCTRL 0x0000 #define OMAP4_PM_PWSTST 0x0004 - -/* PRM */ - /* PRM.OCP_SOCKET_PRM register offsets */ #define OMAP4_REVISION_PRM_OFFSET 0x0000 -#define OMAP4430_REVISION_PRM OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0000) #define OMAP4_PRM_IRQSTATUS_MPU_OFFSET 0x0010 #define OMAP4430_PRM_IRQSTATUS_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0010) #define OMAP4_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 -#define OMAP4430_PRM_IRQSTATUS_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0014) #define OMAP4_PRM_IRQENABLE_MPU_OFFSET 0x0018 #define OMAP4430_PRM_IRQENABLE_MPU OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0018) -#define OMAP4_PRM_IRQENABLE_MPU_2_OFFSET 0x001c -#define OMAP4430_PRM_IRQENABLE_MPU_2 OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x001c) -#define OMAP4_PRM_IRQSTATUS_DUCATI_OFFSET 0x0020 -#define OMAP4430_PRM_IRQSTATUS_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0020) -#define OMAP4_PRM_IRQENABLE_DUCATI_OFFSET 0x0028 -#define OMAP4430_PRM_IRQENABLE_DUCATI OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0028) -#define OMAP4_PRM_IRQSTATUS_TESLA_OFFSET 0x0030 -#define OMAP4430_PRM_IRQSTATUS_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0030) -#define OMAP4_PRM_IRQENABLE_TESLA_OFFSET 0x0038 -#define OMAP4430_PRM_IRQENABLE_TESLA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0038) -#define OMAP4_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_PRM_PROFILING_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_OCP_SOCKET_INST, 0x0040) - -/* PRM.CKGEN_PRM register offsets */ -#define OMAP4_CM_ABE_DSS_SYS_CLKSEL_OFFSET 0x0000 -#define OMAP4430_CM_ABE_DSS_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0000) -#define OMAP4_CM_L4_WKUP_CLKSEL_OFFSET 0x0008 -#define OMAP4430_CM_L4_WKUP_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0008) -#define OMAP4_CM_ABE_PLL_REF_CLKSEL_OFFSET 0x000c -#define OMAP4430_CM_ABE_PLL_REF_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x000c) -#define OMAP4_CM_SYS_CLKSEL_OFFSET 0x0010 -#define OMAP4430_CM_SYS_CLKSEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CKGEN_INST, 0x0010) /* PRM.MPU_PRM register offsets */ -#define OMAP4_PM_MPU_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_MPU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0000) -#define OMAP4_PM_MPU_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_MPU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0004) -#define OMAP4_RM_MPU_RSTST_OFFSET 0x0014 -#define OMAP4430_RM_MPU_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0014) #define OMAP4_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_MPU_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_MPU_INST, 0x0024) - -/* PRM.TESLA_PRM register offsets */ -#define OMAP4_PM_TESLA_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_TESLA_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0000) -#define OMAP4_PM_TESLA_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_TESLA_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0004) -#define OMAP4_RM_TESLA_RSTCTRL_OFFSET 0x0010 -#define OMAP4430_RM_TESLA_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0010) -#define OMAP4_RM_TESLA_RSTST_OFFSET 0x0014 -#define OMAP4430_RM_TESLA_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0014) -#define OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_TESLA_TESLA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_TESLA_INST, 0x0024) - -/* PRM.ABE_PRM register offsets */ -#define OMAP4_PM_ABE_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_ABE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0000) -#define OMAP4_PM_ABE_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_ABE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0004) -#define OMAP4_RM_ABE_AESS_CONTEXT_OFFSET 0x002c -#define OMAP4430_RM_ABE_AESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x002c) -#define OMAP4_PM_ABE_PDM_WKDEP_OFFSET 0x0030 -#define OMAP4430_PM_ABE_PDM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0030) -#define OMAP4_RM_ABE_PDM_CONTEXT_OFFSET 0x0034 -#define OMAP4430_RM_ABE_PDM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0034) -#define OMAP4_PM_ABE_DMIC_WKDEP_OFFSET 0x0038 -#define OMAP4430_PM_ABE_DMIC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0038) -#define OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c -#define OMAP4430_RM_ABE_DMIC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x003c) -#define OMAP4_PM_ABE_MCASP_WKDEP_OFFSET 0x0040 -#define OMAP4430_PM_ABE_MCASP_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0040) -#define OMAP4_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044 -#define OMAP4430_RM_ABE_MCASP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0044) -#define OMAP4_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048 -#define OMAP4430_PM_ABE_MCBSP1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0048) -#define OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c -#define OMAP4430_RM_ABE_MCBSP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x004c) -#define OMAP4_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050 -#define OMAP4430_PM_ABE_MCBSP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0050) -#define OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054 -#define OMAP4430_RM_ABE_MCBSP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0054) -#define OMAP4_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058 -#define OMAP4430_PM_ABE_MCBSP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0058) -#define OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c -#define OMAP4430_RM_ABE_MCBSP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x005c) -#define OMAP4_PM_ABE_SLIMBUS_WKDEP_OFFSET 0x0060 -#define OMAP4430_PM_ABE_SLIMBUS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0060) -#define OMAP4_RM_ABE_SLIMBUS_CONTEXT_OFFSET 0x0064 -#define OMAP4430_RM_ABE_SLIMBUS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0064) -#define OMAP4_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068 -#define OMAP4430_PM_ABE_TIMER5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0068) -#define OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c -#define OMAP4430_RM_ABE_TIMER5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x006c) -#define OMAP4_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070 -#define OMAP4430_PM_ABE_TIMER6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0070) -#define OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074 -#define OMAP4430_RM_ABE_TIMER6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0074) -#define OMAP4_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078 -#define OMAP4430_PM_ABE_TIMER7_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0078) -#define OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c -#define OMAP4430_RM_ABE_TIMER7_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x007c) -#define OMAP4_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080 -#define OMAP4430_PM_ABE_TIMER8_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0080) -#define OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084 -#define OMAP4430_RM_ABE_TIMER8_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0084) -#define OMAP4_PM_ABE_WDT3_WKDEP_OFFSET 0x0088 -#define OMAP4430_PM_ABE_WDT3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x0088) -#define OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET 0x008c -#define OMAP4430_RM_ABE_WDT3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ABE_INST, 0x008c) - -/* PRM.ALWAYS_ON_PRM register offsets */ -#define OMAP4_RM_ALWON_MDMINTC_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_ALWON_MDMINTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0024) -#define OMAP4_PM_ALWON_SR_MPU_WKDEP_OFFSET 0x0028 -#define OMAP4430_PM_ALWON_SR_MPU_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0028) -#define OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET 0x002c -#define OMAP4430_RM_ALWON_SR_MPU_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x002c) -#define OMAP4_PM_ALWON_SR_IVA_WKDEP_OFFSET 0x0030 -#define OMAP4430_PM_ALWON_SR_IVA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0030) -#define OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET 0x0034 -#define OMAP4430_RM_ALWON_SR_IVA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0034) -#define OMAP4_PM_ALWON_SR_CORE_WKDEP_OFFSET 0x0038 -#define OMAP4430_PM_ALWON_SR_CORE_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x0038) -#define OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET 0x003c -#define OMAP4430_RM_ALWON_SR_CORE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_ALWAYS_ON_INST, 0x003c) - -/* PRM.CORE_PRM register offsets */ -#define OMAP4_PM_CORE_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_CORE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0000) -#define OMAP4_PM_CORE_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_CORE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0004) -#define OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_L3_1_L3_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0024) -#define OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET 0x0124 -#define OMAP4430_RM_L3_2_L3_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0124) -#define OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET 0x012c -#define OMAP4430_RM_L3_2_GPMC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x012c) -#define OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET 0x0134 -#define OMAP4430_RM_L3_2_OCMC_RAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0134) -#define OMAP4_RM_DUCATI_RSTCTRL_OFFSET 0x0210 -#define OMAP4430_RM_DUCATI_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0210) -#define OMAP4_RM_DUCATI_RSTST_OFFSET 0x0214 -#define OMAP4430_RM_DUCATI_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0214) -#define OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET 0x0224 -#define OMAP4430_RM_DUCATI_DUCATI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0224) -#define OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET 0x0324 -#define OMAP4430_RM_SDMA_SDMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0324) -#define OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET 0x0424 -#define OMAP4430_RM_MEMIF_DMM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0424) -#define OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET 0x042c -#define OMAP4430_RM_MEMIF_EMIF_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x042c) -#define OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET 0x0434 -#define OMAP4430_RM_MEMIF_EMIF_1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0434) -#define OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET 0x043c -#define OMAP4430_RM_MEMIF_EMIF_2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x043c) -#define OMAP4_RM_MEMIF_DLL_CONTEXT_OFFSET 0x0444 -#define OMAP4430_RM_MEMIF_DLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0444) -#define OMAP4_RM_MEMIF_EMIF_H1_CONTEXT_OFFSET 0x0454 -#define OMAP4430_RM_MEMIF_EMIF_H1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0454) -#define OMAP4_RM_MEMIF_EMIF_H2_CONTEXT_OFFSET 0x045c -#define OMAP4430_RM_MEMIF_EMIF_H2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x045c) -#define OMAP4_RM_MEMIF_DLL_H_CONTEXT_OFFSET 0x0464 -#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464) -#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524 -#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524) -#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c -#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c) -#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534 -#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534) -#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 -#define OMAP4430_RM_L4CFG_L4_CFG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0624) -#define OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET 0x062c -#define OMAP4430_RM_L4CFG_HW_SEM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x062c) -#define OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634 -#define OMAP4430_RM_L4CFG_MAILBOX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0634) -#define OMAP4_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c -#define OMAP4430_RM_L4CFG_SAR_ROM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x063c) -#define OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET 0x0724 -#define OMAP4430_RM_L3INSTR_L3_3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0724) -#define OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c -#define OMAP4430_RM_L3INSTR_L3_INSTR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x072c) -#define OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET 0x0744 -#define OMAP4430_RM_L3INSTR_OCP_WP1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0744) - -/* PRM.IVAHD_PRM register offsets */ -#define OMAP4_PM_IVAHD_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_IVAHD_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0000) -#define OMAP4_PM_IVAHD_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_IVAHD_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0004) -#define OMAP4_RM_IVAHD_RSTCTRL_OFFSET 0x0010 -#define OMAP4430_RM_IVAHD_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0010) -#define OMAP4_RM_IVAHD_RSTST_OFFSET 0x0014 -#define OMAP4430_RM_IVAHD_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0014) -#define OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_IVAHD_IVAHD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x0024) -#define OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET 0x002c -#define OMAP4430_RM_IVAHD_SL2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_IVAHD_INST, 0x002c) - -/* PRM.CAM_PRM register offsets */ -#define OMAP4_PM_CAM_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_CAM_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0000) -#define OMAP4_PM_CAM_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_CAM_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0004) -#define OMAP4_RM_CAM_ISS_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_CAM_ISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x0024) -#define OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c -#define OMAP4430_RM_CAM_FDIF_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CAM_INST, 0x002c) - -/* PRM.DSS_PRM register offsets */ -#define OMAP4_PM_DSS_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_DSS_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0000) -#define OMAP4_PM_DSS_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_DSS_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0004) -#define OMAP4_PM_DSS_DSS_WKDEP_OFFSET 0x0020 -#define OMAP4430_PM_DSS_DSS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0020) -#define OMAP4_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_DSS_DSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x0024) -#define OMAP4_RM_DSS_DEISS_CONTEXT_OFFSET 0x002c -#define OMAP4430_RM_DSS_DEISS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DSS_INST, 0x002c) - -/* PRM.GFX_PRM register offsets */ -#define OMAP4_PM_GFX_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_GFX_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0000) -#define OMAP4_PM_GFX_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_GFX_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0004) -#define OMAP4_RM_GFX_GFX_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_GFX_GFX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_GFX_INST, 0x0024) - -/* PRM.L3INIT_PRM register offsets */ -#define OMAP4_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_L3INIT_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0000) -#define OMAP4_PM_L3INIT_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_L3INIT_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0004) -#define OMAP4_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 -#define OMAP4430_PM_L3INIT_MMC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0028) -#define OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c -#define OMAP4430_RM_L3INIT_MMC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x002c) -#define OMAP4_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 -#define OMAP4430_PM_L3INIT_MMC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0030) -#define OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 -#define OMAP4430_RM_L3INIT_MMC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0034) -#define OMAP4_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038 -#define OMAP4430_PM_L3INIT_HSI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0038) -#define OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c -#define OMAP4430_RM_L3INIT_HSI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x003c) -#define OMAP4_PM_L3INIT_UNIPRO1_WKDEP_OFFSET 0x0040 -#define OMAP4430_PM_L3INIT_UNIPRO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0040) -#define OMAP4_RM_L3INIT_UNIPRO1_CONTEXT_OFFSET 0x0044 -#define OMAP4430_RM_L3INIT_UNIPRO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0044) -#define OMAP4_PM_L3INIT_USB_HOST_WKDEP_OFFSET 0x0058 -#define OMAP4430_PM_L3INIT_USB_HOST_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0058) -#define OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET 0x005c -#define OMAP4430_RM_L3INIT_USB_HOST_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x005c) -#define OMAP4_PM_L3INIT_USB_OTG_WKDEP_OFFSET 0x0060 -#define OMAP4430_PM_L3INIT_USB_OTG_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0060) -#define OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET 0x0064 -#define OMAP4430_RM_L3INIT_USB_OTG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0064) -#define OMAP4_PM_L3INIT_USB_TLL_WKDEP_OFFSET 0x0068 -#define OMAP4430_PM_L3INIT_USB_TLL_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0068) -#define OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET 0x006c -#define OMAP4430_RM_L3INIT_USB_TLL_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x006c) -#define OMAP4_RM_L3INIT_P1500_CONTEXT_OFFSET 0x007c -#define OMAP4430_RM_L3INIT_P1500_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x007c) -#define OMAP4_RM_L3INIT_EMAC_CONTEXT_OFFSET 0x0084 -#define OMAP4430_RM_L3INIT_EMAC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0084) -#define OMAP4_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 -#define OMAP4430_PM_L3INIT_SATA_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0088) -#define OMAP4_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c -#define OMAP4430_RM_L3INIT_SATA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x008c) -#define OMAP4_RM_L3INIT_TPPSS_CONTEXT_OFFSET 0x0094 -#define OMAP4430_RM_L3INIT_TPPSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0094) -#define OMAP4_PM_L3INIT_PCIESS_WKDEP_OFFSET 0x0098 -#define OMAP4430_PM_L3INIT_PCIESS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x0098) -#define OMAP4_RM_L3INIT_PCIESS_CONTEXT_OFFSET 0x009c -#define OMAP4430_RM_L3INIT_PCIESS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x009c) -#define OMAP4_RM_L3INIT_CCPTX_CONTEXT_OFFSET 0x00ac -#define OMAP4430_RM_L3INIT_CCPTX_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00ac) -#define OMAP4_PM_L3INIT_XHPI_WKDEP_OFFSET 0x00c0 -#define OMAP4430_PM_L3INIT_XHPI_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c0) -#define OMAP4_RM_L3INIT_XHPI_CONTEXT_OFFSET 0x00c4 -#define OMAP4430_RM_L3INIT_XHPI_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c4) -#define OMAP4_PM_L3INIT_MMC6_WKDEP_OFFSET 0x00c8 -#define OMAP4430_PM_L3INIT_MMC6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00c8) -#define OMAP4_RM_L3INIT_MMC6_CONTEXT_OFFSET 0x00cc -#define OMAP4430_RM_L3INIT_MMC6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00cc) -#define OMAP4_PM_L3INIT_USB_HOST_FS_WKDEP_OFFSET 0x00d0 -#define OMAP4430_PM_L3INIT_USB_HOST_FS_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d0) -#define OMAP4_RM_L3INIT_USB_HOST_FS_CONTEXT_OFFSET 0x00d4 -#define OMAP4430_RM_L3INIT_USB_HOST_FS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00d4) -#define OMAP4_RM_L3INIT_USBPHYOCP2SCP_CONTEXT_OFFSET 0x00e4 -#define OMAP4430_RM_L3INIT_USBPHYOCP2SCP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L3INIT_INST, 0x00e4) - -/* PRM.L4PER_PRM register offsets */ -#define OMAP4_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_L4PER_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0000) -#define OMAP4_PM_L4PER_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_L4PER_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0004) -#define OMAP4_RM_L4PER_ADC_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_L4PER_ADC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0024) -#define OMAP4_PM_L4PER_DMTIMER10_WKDEP_OFFSET 0x0028 -#define OMAP4430_PM_L4PER_DMTIMER10_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0028) -#define OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET 0x002c -#define OMAP4430_RM_L4PER_DMTIMER10_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x002c) -#define OMAP4_PM_L4PER_DMTIMER11_WKDEP_OFFSET 0x0030 -#define OMAP4430_PM_L4PER_DMTIMER11_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0030) -#define OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET 0x0034 -#define OMAP4430_RM_L4PER_DMTIMER11_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0034) -#define OMAP4_PM_L4PER_DMTIMER2_WKDEP_OFFSET 0x0038 -#define OMAP4430_PM_L4PER_DMTIMER2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0038) -#define OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET 0x003c -#define OMAP4430_RM_L4PER_DMTIMER2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x003c) -#define OMAP4_PM_L4PER_DMTIMER3_WKDEP_OFFSET 0x0040 -#define OMAP4430_PM_L4PER_DMTIMER3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0040) -#define OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET 0x0044 -#define OMAP4430_RM_L4PER_DMTIMER3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0044) -#define OMAP4_PM_L4PER_DMTIMER4_WKDEP_OFFSET 0x0048 -#define OMAP4430_PM_L4PER_DMTIMER4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0048) -#define OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET 0x004c -#define OMAP4430_RM_L4PER_DMTIMER4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x004c) -#define OMAP4_PM_L4PER_DMTIMER9_WKDEP_OFFSET 0x0050 -#define OMAP4430_PM_L4PER_DMTIMER9_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0050) -#define OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET 0x0054 -#define OMAP4430_RM_L4PER_DMTIMER9_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0054) -#define OMAP4_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c -#define OMAP4430_RM_L4PER_ELM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x005c) -#define OMAP4_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 -#define OMAP4430_PM_L4PER_GPIO2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0060) -#define OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 -#define OMAP4430_RM_L4PER_GPIO2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0064) -#define OMAP4_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 -#define OMAP4430_PM_L4PER_GPIO3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0068) -#define OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c -#define OMAP4430_RM_L4PER_GPIO3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x006c) -#define OMAP4_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 -#define OMAP4430_PM_L4PER_GPIO4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0070) -#define OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 -#define OMAP4430_RM_L4PER_GPIO4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0074) -#define OMAP4_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 -#define OMAP4430_PM_L4PER_GPIO5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0078) -#define OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c -#define OMAP4430_RM_L4PER_GPIO5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x007c) -#define OMAP4_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 -#define OMAP4430_PM_L4PER_GPIO6_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0080) -#define OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 -#define OMAP4430_RM_L4PER_GPIO6_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0084) -#define OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c -#define OMAP4430_RM_L4PER_HDQ1W_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x008c) -#define OMAP4_PM_L4PER_HECC1_WKDEP_OFFSET 0x0090 -#define OMAP4430_PM_L4PER_HECC1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0090) -#define OMAP4_RM_L4PER_HECC1_CONTEXT_OFFSET 0x0094 -#define OMAP4430_RM_L4PER_HECC1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0094) -#define OMAP4_PM_L4PER_HECC2_WKDEP_OFFSET 0x0098 -#define OMAP4430_PM_L4PER_HECC2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0098) -#define OMAP4_RM_L4PER_HECC2_CONTEXT_OFFSET 0x009c -#define OMAP4430_RM_L4PER_HECC2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x009c) -#define OMAP4_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 -#define OMAP4430_PM_L4PER_I2C1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a0) -#define OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 -#define OMAP4430_RM_L4PER_I2C1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a4) -#define OMAP4_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 -#define OMAP4430_PM_L4PER_I2C2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00a8) -#define OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac -#define OMAP4430_RM_L4PER_I2C2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ac) -#define OMAP4_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 -#define OMAP4430_PM_L4PER_I2C3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b0) -#define OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 -#define OMAP4430_RM_L4PER_I2C3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b4) -#define OMAP4_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 -#define OMAP4430_PM_L4PER_I2C4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00b8) -#define OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc -#define OMAP4430_RM_L4PER_I2C4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00bc) -#define OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x00c0 -#define OMAP4430_RM_L4PER_L4_PER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00c0) -#define OMAP4_PM_L4PER_MCASP2_WKDEP_OFFSET 0x00d0 -#define OMAP4430_PM_L4PER_MCASP2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d0) -#define OMAP4_RM_L4PER_MCASP2_CONTEXT_OFFSET 0x00d4 -#define OMAP4430_RM_L4PER_MCASP2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d4) -#define OMAP4_PM_L4PER_MCASP3_WKDEP_OFFSET 0x00d8 -#define OMAP4430_PM_L4PER_MCASP3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00d8) -#define OMAP4_RM_L4PER_MCASP3_CONTEXT_OFFSET 0x00dc -#define OMAP4430_RM_L4PER_MCASP3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00dc) -#define OMAP4_PM_L4PER_MCBSP4_WKDEP_OFFSET 0x00e0 -#define OMAP4430_PM_L4PER_MCBSP4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e0) -#define OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET 0x00e4 -#define OMAP4430_RM_L4PER_MCBSP4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00e4) -#define OMAP4_RM_L4PER_MGATE_CONTEXT_OFFSET 0x00ec -#define OMAP4430_RM_L4PER_MGATE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00ec) -#define OMAP4_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 -#define OMAP4430_PM_L4PER_MCSPI1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f0) -#define OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 -#define OMAP4430_RM_L4PER_MCSPI1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f4) -#define OMAP4_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 -#define OMAP4430_PM_L4PER_MCSPI2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00f8) -#define OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc -#define OMAP4430_RM_L4PER_MCSPI2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x00fc) -#define OMAP4_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 -#define OMAP4430_PM_L4PER_MCSPI3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0100) -#define OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 -#define OMAP4430_RM_L4PER_MCSPI3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0104) -#define OMAP4_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 -#define OMAP4430_PM_L4PER_MCSPI4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0108) -#define OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c -#define OMAP4430_RM_L4PER_MCSPI4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x010c) -#define OMAP4_PM_L4PER_MMCSD3_WKDEP_OFFSET 0x0120 -#define OMAP4430_PM_L4PER_MMCSD3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0120) -#define OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET 0x0124 -#define OMAP4430_RM_L4PER_MMCSD3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0124) -#define OMAP4_PM_L4PER_MMCSD4_WKDEP_OFFSET 0x0128 -#define OMAP4430_PM_L4PER_MMCSD4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0128) -#define OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET 0x012c -#define OMAP4430_RM_L4PER_MMCSD4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x012c) -#define OMAP4_RM_L4PER_MSPROHG_CONTEXT_OFFSET 0x0134 -#define OMAP4430_RM_L4PER_MSPROHG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0134) -#define OMAP4_PM_L4PER_SLIMBUS2_WKDEP_OFFSET 0x0138 -#define OMAP4430_PM_L4PER_SLIMBUS2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0138) -#define OMAP4_RM_L4PER_SLIMBUS2_CONTEXT_OFFSET 0x013c -#define OMAP4430_RM_L4PER_SLIMBUS2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x013c) -#define OMAP4_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 -#define OMAP4430_PM_L4PER_UART1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0140) -#define OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 -#define OMAP4430_RM_L4PER_UART1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0144) -#define OMAP4_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 -#define OMAP4430_PM_L4PER_UART2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0148) -#define OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c -#define OMAP4430_RM_L4PER_UART2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x014c) -#define OMAP4_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 -#define OMAP4430_PM_L4PER_UART3_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0150) -#define OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 -#define OMAP4430_RM_L4PER_UART3_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0154) -#define OMAP4_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 -#define OMAP4430_PM_L4PER_UART4_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0158) -#define OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c -#define OMAP4430_RM_L4PER_UART4_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x015c) -#define OMAP4_PM_L4PER_MMCSD5_WKDEP_OFFSET 0x0160 -#define OMAP4430_PM_L4PER_MMCSD5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0160) -#define OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET 0x0164 -#define OMAP4430_RM_L4PER_MMCSD5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0164) -#define OMAP4_PM_L4PER_I2C5_WKDEP_OFFSET 0x0168 -#define OMAP4430_PM_L4PER_I2C5_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x0168) -#define OMAP4_RM_L4PER_I2C5_CONTEXT_OFFSET 0x016c -#define OMAP4430_RM_L4PER_I2C5_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x016c) -#define OMAP4_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 -#define OMAP4430_RM_L4SEC_AES1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01a4) -#define OMAP4_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac -#define OMAP4430_RM_L4SEC_AES2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01ac) -#define OMAP4_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 -#define OMAP4430_RM_L4SEC_DES3DES_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01b4) -#define OMAP4_RM_L4SEC_PKAEIP29_CONTEXT_OFFSET 0x01bc -#define OMAP4430_RM_L4SEC_PKAEIP29_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01bc) -#define OMAP4_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 -#define OMAP4430_RM_L4SEC_RNG_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01c4) -#define OMAP4_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc -#define OMAP4430_RM_L4SEC_SHA2MD51_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01cc) -#define OMAP4_RM_L4SEC_CRYPTODMA_CONTEXT_OFFSET 0x01dc -#define OMAP4430_RM_L4SEC_CRYPTODMA_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_L4PER_INST, 0x01dc) - -/* PRM.CEFUSE_PRM register offsets */ -#define OMAP4_PM_CEFUSE_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_CEFUSE_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0000) -#define OMAP4_PM_CEFUSE_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_CEFUSE_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0004) -#define OMAP4_RM_CEFUSE_CEFUSE_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_CEFUSE_CEFUSE_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CEFUSE_INST, 0x0024) - -/* PRM.WKUP_PRM register offsets */ -#define OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_WKUP_L4WKUP_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0024) -#define OMAP4_RM_WKUP_WDT1_CONTEXT_OFFSET 0x002c -#define OMAP4430_RM_WKUP_WDT1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x002c) -#define OMAP4_PM_WKUP_WDT2_WKDEP_OFFSET 0x0030 -#define OMAP4430_PM_WKUP_WDT2_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0030) -#define OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET 0x0034 -#define OMAP4430_RM_WKUP_WDT2_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0034) -#define OMAP4_PM_WKUP_GPIO1_WKDEP_OFFSET 0x0038 -#define OMAP4430_PM_WKUP_GPIO1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0038) -#define OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET 0x003c -#define OMAP4430_RM_WKUP_GPIO1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x003c) -#define OMAP4_PM_WKUP_TIMER1_WKDEP_OFFSET 0x0040 -#define OMAP4430_PM_WKUP_TIMER1_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0040) -#define OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET 0x0044 -#define OMAP4430_RM_WKUP_TIMER1_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0044) -#define OMAP4_PM_WKUP_TIMER12_WKDEP_OFFSET 0x0048 -#define OMAP4430_PM_WKUP_TIMER12_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0048) -#define OMAP4_RM_WKUP_TIMER12_CONTEXT_OFFSET 0x004c -#define OMAP4430_RM_WKUP_TIMER12_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x004c) -#define OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET 0x0054 -#define OMAP4430_RM_WKUP_SYNCTIMER_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0054) -#define OMAP4_PM_WKUP_USIM_WKDEP_OFFSET 0x0058 -#define OMAP4430_PM_WKUP_USIM_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0058) -#define OMAP4_RM_WKUP_USIM_CONTEXT_OFFSET 0x005c -#define OMAP4430_RM_WKUP_USIM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x005c) -#define OMAP4_RM_WKUP_SARRAM_CONTEXT_OFFSET 0x0064 -#define OMAP4430_RM_WKUP_SARRAM_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0064) -#define OMAP4_PM_WKUP_KEYBOARD_WKDEP_OFFSET 0x0078 -#define OMAP4430_PM_WKUP_KEYBOARD_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0078) -#define OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET 0x007c -#define OMAP4430_RM_WKUP_KEYBOARD_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x007c) -#define OMAP4_PM_WKUP_RTC_WKDEP_OFFSET 0x0080 -#define OMAP4430_PM_WKUP_RTC_WKDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0080) -#define OMAP4_RM_WKUP_RTC_CONTEXT_OFFSET 0x0084 -#define OMAP4430_RM_WKUP_RTC_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_INST, 0x0084) - -/* PRM.WKUP_CM register offsets */ -#define OMAP4_CM_WKUP_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_WKUP_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0000) -#define OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_WKUP_L4WKUP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0020) -#define OMAP4_CM_WKUP_WDT1_CLKCTRL_OFFSET 0x0028 -#define OMAP4430_CM_WKUP_WDT1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0028) -#define OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET 0x0030 -#define OMAP4430_CM_WKUP_WDT2_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0030) -#define OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET 0x0038 -#define OMAP4430_CM_WKUP_GPIO1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0038) -#define OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET 0x0040 -#define OMAP4430_CM_WKUP_TIMER1_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0040) -#define OMAP4_CM_WKUP_TIMER12_CLKCTRL_OFFSET 0x0048 -#define OMAP4430_CM_WKUP_TIMER12_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0048) -#define OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET 0x0050 -#define OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0050) -#define OMAP4_CM_WKUP_USIM_CLKCTRL_OFFSET 0x0058 -#define OMAP4430_CM_WKUP_USIM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0058) -#define OMAP4_CM_WKUP_SARRAM_CLKCTRL_OFFSET 0x0060 -#define OMAP4430_CM_WKUP_SARRAM_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0060) -#define OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET 0x0078 -#define OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0078) -#define OMAP4_CM_WKUP_RTC_CLKCTRL_OFFSET 0x0080 -#define OMAP4430_CM_WKUP_RTC_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0080) -#define OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET 0x0088 -#define OMAP4430_CM_WKUP_BANDGAP_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_WKUP_CM_INST, 0x0088) - -/* PRM.EMU_PRM register offsets */ -#define OMAP4_PM_EMU_PWRSTCTRL_OFFSET 0x0000 -#define OMAP4430_PM_EMU_PWRSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0000) -#define OMAP4_PM_EMU_PWRSTST_OFFSET 0x0004 -#define OMAP4430_PM_EMU_PWRSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0004) -#define OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 -#define OMAP4430_RM_EMU_DEBUGSS_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_INST, 0x0024) - -/* PRM.EMU_CM register offsets */ -#define OMAP4_CM_EMU_CLKSTCTRL_OFFSET 0x0000 -#define OMAP4430_CM_EMU_CLKSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0000) -#define OMAP4_CM_EMU_DYNAMICDEP_OFFSET 0x0008 -#define OMAP4430_CM_EMU_DYNAMICDEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0008) -#define OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 -#define OMAP4430_CM_EMU_DEBUGSS_CLKCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_EMU_CM_INST, 0x0020) /* PRM.DEVICE_PRM register offsets */ #define OMAP4_PRM_RSTCTRL_OFFSET 0x0000 -#define OMAP4430_PRM_RSTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0000) -#define OMAP4_PRM_RSTST_OFFSET 0x0004 -#define OMAP4430_PRM_RSTST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0004) -#define OMAP4_PRM_RSTTIME_OFFSET 0x0008 -#define OMAP4430_PRM_RSTTIME OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0008) -#define OMAP4_PRM_CLKREQCTRL_OFFSET 0x000c -#define OMAP4430_PRM_CLKREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x000c) #define OMAP4_PRM_VOLTCTRL_OFFSET 0x0010 -#define OMAP4430_PRM_VOLTCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0010) -#define OMAP4_PRM_PWRREQCTRL_OFFSET 0x0014 -#define OMAP4430_PRM_PWRREQCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0014) -#define OMAP4_PRM_PSCON_COUNT_OFFSET 0x0018 -#define OMAP4430_PRM_PSCON_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0018) -#define OMAP4_PRM_IO_COUNT_OFFSET 0x001c -#define OMAP4430_PRM_IO_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x001c) #define OMAP4_PRM_IO_PMCTRL_OFFSET 0x0020 -#define OMAP4430_PRM_IO_PMCTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0020) -#define OMAP4_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 -#define OMAP4430_PRM_VOLTSETUP_WARMRESET OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0024) #define OMAP4_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 -#define OMAP4430_PRM_VOLTSETUP_CORE_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0028) #define OMAP4_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c -#define OMAP4430_PRM_VOLTSETUP_MPU_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x002c) #define OMAP4_PRM_VOLTSETUP_IVA_OFF_OFFSET 0x0030 -#define OMAP4430_PRM_VOLTSETUP_IVA_OFF OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0030) #define OMAP4_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 -#define OMAP4430_PRM_VOLTSETUP_CORE_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0034) #define OMAP4_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 -#define OMAP4430_PRM_VOLTSETUP_MPU_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0038) #define OMAP4_PRM_VOLTSETUP_IVA_RET_SLEEP_OFFSET 0x003c -#define OMAP4430_PRM_VOLTSETUP_IVA_RET_SLEEP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x003c) #define OMAP4_PRM_VP_CORE_CONFIG_OFFSET 0x0040 -#define OMAP4430_PRM_VP_CORE_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0040) #define OMAP4_PRM_VP_CORE_STATUS_OFFSET 0x0044 -#define OMAP4430_PRM_VP_CORE_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0044) #define OMAP4_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 -#define OMAP4430_PRM_VP_CORE_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0048) #define OMAP4_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c -#define OMAP4430_PRM_VP_CORE_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x004c) #define OMAP4_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 -#define OMAP4430_PRM_VP_CORE_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0050) #define OMAP4_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 -#define OMAP4430_PRM_VP_CORE_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0054) #define OMAP4_PRM_VP_MPU_CONFIG_OFFSET 0x0058 -#define OMAP4430_PRM_VP_MPU_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0058) #define OMAP4_PRM_VP_MPU_STATUS_OFFSET 0x005c -#define OMAP4430_PRM_VP_MPU_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x005c) #define OMAP4_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 -#define OMAP4430_PRM_VP_MPU_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0060) #define OMAP4_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 -#define OMAP4430_PRM_VP_MPU_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0064) #define OMAP4_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 -#define OMAP4430_PRM_VP_MPU_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0068) #define OMAP4_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c -#define OMAP4430_PRM_VP_MPU_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x006c) #define OMAP4_PRM_VP_IVA_CONFIG_OFFSET 0x0070 -#define OMAP4430_PRM_VP_IVA_CONFIG OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0070) #define OMAP4_PRM_VP_IVA_STATUS_OFFSET 0x0074 -#define OMAP4430_PRM_VP_IVA_STATUS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0074) #define OMAP4_PRM_VP_IVA_VLIMITTO_OFFSET 0x0078 -#define OMAP4430_PRM_VP_IVA_VLIMITTO OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0078) #define OMAP4_PRM_VP_IVA_VOLTAGE_OFFSET 0x007c -#define OMAP4430_PRM_VP_IVA_VOLTAGE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x007c) #define OMAP4_PRM_VP_IVA_VSTEPMAX_OFFSET 0x0080 -#define OMAP4430_PRM_VP_IVA_VSTEPMAX OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0080) #define OMAP4_PRM_VP_IVA_VSTEPMIN_OFFSET 0x0084 -#define OMAP4430_PRM_VP_IVA_VSTEPMIN OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0084) #define OMAP4_PRM_VC_SMPS_SA_OFFSET 0x0088 -#define OMAP4430_PRM_VC_SMPS_SA OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0088) #define OMAP4_PRM_VC_VAL_SMPS_RA_VOL_OFFSET 0x008c -#define OMAP4430_PRM_VC_VAL_SMPS_RA_VOL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x008c) #define OMAP4_PRM_VC_VAL_SMPS_RA_CMD_OFFSET 0x0090 -#define OMAP4430_PRM_VC_VAL_SMPS_RA_CMD OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0090) #define OMAP4_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 -#define OMAP4430_PRM_VC_VAL_CMD_VDD_CORE_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0094) #define OMAP4_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x0098 -#define OMAP4430_PRM_VC_VAL_CMD_VDD_MPU_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x0098) #define OMAP4_PRM_VC_VAL_CMD_VDD_IVA_L_OFFSET 0x009c -#define OMAP4430_PRM_VC_VAL_CMD_VDD_IVA_L OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x009c) #define OMAP4_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 -#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0) #define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4 -#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4) #define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8 -#define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8) #define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac -#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac) -#define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0 -#define OMAP4430_PRM_SRAM_COUNT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b0) -#define OMAP4_PRM_SRAM_WKUP_SETUP_OFFSET 0x00b4 -#define OMAP4430_PRM_SRAM_WKUP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b4) -#define OMAP4_PRM_LDO_SRAM_CORE_SETUP_OFFSET 0x00b8 -#define OMAP4430_PRM_LDO_SRAM_CORE_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00b8) -#define OMAP4_PRM_LDO_SRAM_CORE_CTRL_OFFSET 0x00bc -#define OMAP4430_PRM_LDO_SRAM_CORE_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00bc) -#define OMAP4_PRM_LDO_SRAM_MPU_SETUP_OFFSET 0x00c0 -#define OMAP4430_PRM_LDO_SRAM_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c0) -#define OMAP4_PRM_LDO_SRAM_MPU_CTRL_OFFSET 0x00c4 -#define OMAP4430_PRM_LDO_SRAM_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c4) -#define OMAP4_PRM_LDO_SRAM_IVA_SETUP_OFFSET 0x00c8 -#define OMAP4430_PRM_LDO_SRAM_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00c8) -#define OMAP4_PRM_LDO_SRAM_IVA_CTRL_OFFSET 0x00cc -#define OMAP4430_PRM_LDO_SRAM_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00cc) -#define OMAP4_PRM_LDO_ABB_MPU_SETUP_OFFSET 0x00d0 -#define OMAP4430_PRM_LDO_ABB_MPU_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d0) -#define OMAP4_PRM_LDO_ABB_MPU_CTRL_OFFSET 0x00d4 -#define OMAP4430_PRM_LDO_ABB_MPU_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d4) -#define OMAP4_PRM_LDO_ABB_IVA_SETUP_OFFSET 0x00d8 -#define OMAP4430_PRM_LDO_ABB_IVA_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00d8) -#define OMAP4_PRM_LDO_ABB_IVA_CTRL_OFFSET 0x00dc -#define OMAP4430_PRM_LDO_ABB_IVA_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00dc) -#define OMAP4_PRM_LDO_BANDGAP_SETUP_OFFSET 0x00e0 -#define OMAP4430_PRM_LDO_BANDGAP_SETUP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e0) -#define OMAP4_PRM_DEVICE_OFF_CTRL_OFFSET 0x00e4 -#define OMAP4430_PRM_DEVICE_OFF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e4) -#define OMAP4_PRM_PHASE1_CNDP_OFFSET 0x00e8 -#define OMAP4430_PRM_PHASE1_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00e8) -#define OMAP4_PRM_PHASE2A_CNDP_OFFSET 0x00ec -#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec) -#define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0 -#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0) -#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4 -#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4) -#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8 -#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8) #endif diff --git a/arch/arm/mach-omap2/prm54xx.h b/arch/arm/mach-omap2/prm54xx.h index 7329d6fcd78b..0b59eeda778d 100644 --- a/arch/arm/mach-omap2/prm54xx.h +++ b/arch/arm/mach-omap2/prm54xx.h @@ -46,372 +46,14 @@ #define OMAP54XX_PRM_EMU_INST 0x1a00 #define OMAP54XX_PRM_EMU_CM_INST 0x1b00 #define OMAP54XX_PRM_DEVICE_INST 0x1c00 -#define OMAP54XX_PRM_INSTR_INST 0x1f00 /* PRM clockdomain register offsets (from instance start) */ #define OMAP54XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 #define OMAP54XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 -/* PRM */ - -/* PRM.OCP_SOCKET_PRM register offsets */ -#define OMAP54XX_REVISION_PRM_OFFSET 0x0000 -#define OMAP54XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010 -#define OMAP54XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 -#define OMAP54XX_PRM_IRQENABLE_MPU_OFFSET 0x0018 -#define OMAP54XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c -#define OMAP54XX_PRM_IRQSTATUS_IPU_OFFSET 0x0020 -#define OMAP54XX_PRM_IRQENABLE_IPU_OFFSET 0x0028 -#define OMAP54XX_PRM_IRQSTATUS_DSP_OFFSET 0x0030 -#define OMAP54XX_PRM_IRQENABLE_DSP_OFFSET 0x0038 -#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 -#define OMAP54XX_CM_PRM_PROFILING_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_OCP_SOCKET_INST, 0x0040) -#define OMAP54XX_PRM_DEBUG_OUT_OFFSET 0x0084 -#define OMAP54XX_PRM_DEBUG_TRANS_CFG_OFFSET 0x0090 -#define OMAP54XX_PRM_DEBUG_OFF_TRANS_OFFSET 0x0094 -#define OMAP54XX_PRM_DEBUG_CORE_RET_TRANS_OFFSET 0x0098 -#define OMAP54XX_PRM_DEBUG_MPU_RET_TRANS_OFFSET 0x009c -#define OMAP54XX_PRM_DEBUG_MM_RET_TRANS_OFFSET 0x00a0 -#define OMAP54XX_PRM_DEBUG_WKUPAON_FD_TRANS_OFFSET 0x00a4 - -/* PRM.CKGEN_PRM register offsets */ -#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS_OFFSET 0x0000 -#define OMAP54XX_CM_CLKSEL_ABE_DSS_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0000) -#define OMAP54XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008 -#define OMAP54XX_CM_CLKSEL_WKUPAON OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0008) -#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c -#define OMAP54XX_CM_CLKSEL_ABE_PLL_REF OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x000c) -#define OMAP54XX_CM_CLKSEL_SYS_OFFSET 0x0010 -#define OMAP54XX_CM_CLKSEL_SYS OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_CKGEN_INST, 0x0010) - -/* PRM.MPU_PRM register offsets */ -#define OMAP54XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 -#define OMAP54XX_PM_MPU_PWRSTST_OFFSET 0x0004 -#define OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 - -/* PRM.DSP_PRM register offsets */ -#define OMAP54XX_PM_DSP_PWRSTCTRL_OFFSET 0x0000 -#define OMAP54XX_PM_DSP_PWRSTST_OFFSET 0x0004 -#define OMAP54XX_RM_DSP_RSTCTRL_OFFSET 0x0010 -#define OMAP54XX_RM_DSP_RSTST_OFFSET 0x0014 -#define OMAP54XX_RM_DSP_DSP_CONTEXT_OFFSET 0x0024 - -/* PRM.ABE_PRM register offsets */ -#define OMAP54XX_PM_ABE_PWRSTCTRL_OFFSET 0x0000 -#define OMAP54XX_PM_ABE_PWRSTST_OFFSET 0x0004 -#define OMAP54XX_RM_ABE_AESS_CONTEXT_OFFSET 0x002c -#define OMAP54XX_PM_ABE_MCPDM_WKDEP_OFFSET 0x0030 -#define OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET 0x0034 -#define OMAP54XX_PM_ABE_DMIC_WKDEP_OFFSET 0x0038 -#define OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET 0x003c -#define OMAP54XX_PM_ABE_MCASP_WKDEP_OFFSET 0x0040 -#define OMAP54XX_RM_ABE_MCASP_CONTEXT_OFFSET 0x0044 -#define OMAP54XX_PM_ABE_MCBSP1_WKDEP_OFFSET 0x0048 -#define OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET 0x004c -#define OMAP54XX_PM_ABE_MCBSP2_WKDEP_OFFSET 0x0050 -#define OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET 0x0054 -#define OMAP54XX_PM_ABE_MCBSP3_WKDEP_OFFSET 0x0058 -#define OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET 0x005c -#define OMAP54XX_PM_ABE_SLIMBUS1_WKDEP_OFFSET 0x0060 -#define OMAP54XX_RM_ABE_SLIMBUS1_CONTEXT_OFFSET 0x0064 -#define OMAP54XX_PM_ABE_TIMER5_WKDEP_OFFSET 0x0068 -#define OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET 0x006c -#define OMAP54XX_PM_ABE_TIMER6_WKDEP_OFFSET 0x0070 -#define OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET 0x0074 -#define OMAP54XX_PM_ABE_TIMER7_WKDEP_OFFSET 0x0078 -#define OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET 0x007c -#define OMAP54XX_PM_ABE_TIMER8_WKDEP_OFFSET 0x0080 -#define OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET 0x0084 -#define OMAP54XX_PM_ABE_WD_TIMER3_WKDEP_OFFSET 0x0088 -#define OMAP54XX_RM_ABE_WD_TIMER3_CONTEXT_OFFSET 0x008c - -/* PRM.COREAON_PRM register offsets */ -#define OMAP54XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0028 -#define OMAP54XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x002c -#define OMAP54XX_PM_COREAON_SMARTREFLEX_MM_WKDEP_OFFSET 0x0030 -#define OMAP54XX_RM_COREAON_SMARTREFLEX_MM_CONTEXT_OFFSET 0x0034 -#define OMAP54XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0038 -#define OMAP54XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x003c - -/* PRM.CORE_PRM register offsets */ -#define OMAP54XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000 -#define OMAP54XX_PM_CORE_PWRSTST_OFFSET 0x0004 -#define OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024 -#define OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET 0x0124 -#define OMAP54XX_RM_L3MAIN2_GPMC_CONTEXT_OFFSET 0x012c -#define OMAP54XX_RM_L3MAIN2_OCMC_RAM_CONTEXT_OFFSET 0x0134 -#define OMAP54XX_RM_IPU_RSTCTRL_OFFSET 0x0210 -#define OMAP54XX_RM_IPU_RSTST_OFFSET 0x0214 -#define OMAP54XX_RM_IPU_IPU_CONTEXT_OFFSET 0x0224 -#define OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324 -#define OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424 -#define OMAP54XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c -#define OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434 -#define OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c -#define OMAP54XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444 -#define OMAP54XX_RM_C2C_C2C_CONTEXT_OFFSET 0x0524 -#define OMAP54XX_RM_C2C_MODEM_ICR_CONTEXT_OFFSET 0x052c -#define OMAP54XX_RM_C2C_C2C_OCP_FW_CONTEXT_OFFSET 0x0534 -#define OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 -#define OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c -#define OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET 0x0634 -#define OMAP54XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c -#define OMAP54XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644 -#define OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET 0x0724 -#define OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c -#define OMAP54XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744 -#define OMAP54XX_RM_MIPIEXT_LLI_CONTEXT_OFFSET 0x0824 -#define OMAP54XX_RM_MIPIEXT_LLI_OCP_FW_CONTEXT_OFFSET 0x082c -#define OMAP54XX_RM_MIPIEXT_MPHY_CONTEXT_OFFSET 0x0834 -#define OMAP54XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0928 -#define OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x092c -#define OMAP54XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0930 -#define OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0934 -#define OMAP54XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0938 -#define OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x093c -#define OMAP54XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0940 -#define OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0944 -#define OMAP54XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0948 -#define OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x094c -#define OMAP54XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0950 -#define OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0954 -#define OMAP54XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x095c -#define OMAP54XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0960 -#define OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0964 -#define OMAP54XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0968 -#define OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x096c -#define OMAP54XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0970 -#define OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0974 -#define OMAP54XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0978 -#define OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x097c -#define OMAP54XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0980 -#define OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0984 -#define OMAP54XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x098c -#define OMAP54XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x09a0 -#define OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x09a4 -#define OMAP54XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x09a8 -#define OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x09ac -#define OMAP54XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x09b0 -#define OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x09b4 -#define OMAP54XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x09b8 -#define OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x09bc -#define OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET 0x09c0 -#define OMAP54XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x09f0 -#define OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x09f4 -#define OMAP54XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x09f8 -#define OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x09fc -#define OMAP54XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0a00 -#define OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0a04 -#define OMAP54XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0a08 -#define OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x0a0c -#define OMAP54XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0a10 -#define OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0a14 -#define OMAP54XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0a18 -#define OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x0a1c -#define OMAP54XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0a20 -#define OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0a24 -#define OMAP54XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0a28 -#define OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x0a2c -#define OMAP54XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0a40 -#define OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0a44 -#define OMAP54XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0a48 -#define OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x0a4c -#define OMAP54XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0a50 -#define OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0a54 -#define OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x0a58 -#define OMAP54XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0a5c -#define OMAP54XX_PM_L4PER_MMC5_WKDEP_OFFSET 0x0a60 -#define OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET 0x0a64 -#define OMAP54XX_PM_L4PER_I2C5_WKDEP_OFFSET 0x0a68 -#define OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET 0x0a6c -#define OMAP54XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0a70 -#define OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0a74 -#define OMAP54XX_PM_L4PER_UART6_WKDEP_OFFSET 0x0a78 -#define OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET 0x0a7c -#define OMAP54XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x0aa4 -#define OMAP54XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x0aac -#define OMAP54XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x0ab4 -#define OMAP54XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x0abc -#define OMAP54XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x0ac4 -#define OMAP54XX_RM_L4SEC_SHA2MD5_CONTEXT_OFFSET 0x0acc -#define OMAP54XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x0adc - -/* PRM.IVA_PRM register offsets */ -#define OMAP54XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000 -#define OMAP54XX_PM_IVA_PWRSTST_OFFSET 0x0004 -#define OMAP54XX_RM_IVA_RSTCTRL_OFFSET 0x0010 -#define OMAP54XX_RM_IVA_RSTST_OFFSET 0x0014 -#define OMAP54XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024 -#define OMAP54XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c - -/* PRM.CAM_PRM register offsets */ -#define OMAP54XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000 -#define OMAP54XX_PM_CAM_PWRSTST_OFFSET 0x0004 -#define OMAP54XX_RM_CAM_ISS_CONTEXT_OFFSET 0x0024 -#define OMAP54XX_RM_CAM_FDIF_CONTEXT_OFFSET 0x002c -#define OMAP54XX_RM_CAM_CAL_CONTEXT_OFFSET 0x0034 - -/* PRM.DSS_PRM register offsets */ -#define OMAP54XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000 -#define OMAP54XX_PM_DSS_PWRSTST_OFFSET 0x0004 -#define OMAP54XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020 -#define OMAP54XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 -#define OMAP54XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034 - -/* PRM.GPU_PRM register offsets */ -#define OMAP54XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000 -#define OMAP54XX_PM_GPU_PWRSTST_OFFSET 0x0004 -#define OMAP54XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024 - -/* PRM.L3INIT_PRM register offsets */ -#define OMAP54XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 -#define OMAP54XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 -#define OMAP54XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 -#define OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c -#define OMAP54XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 -#define OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 -#define OMAP54XX_PM_L3INIT_HSI_WKDEP_OFFSET 0x0038 -#define OMAP54XX_RM_L3INIT_HSI_CONTEXT_OFFSET 0x003c -#define OMAP54XX_PM_L3INIT_UNIPRO2_WKDEP_OFFSET 0x0040 -#define OMAP54XX_RM_L3INIT_UNIPRO2_CONTEXT_OFFSET 0x0044 -#define OMAP54XX_PM_L3INIT_USB_HOST_HS_WKDEP_OFFSET 0x0058 -#define OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET 0x005c -#define OMAP54XX_PM_L3INIT_USB_TLL_HS_WKDEP_OFFSET 0x0068 -#define OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET 0x006c -#define OMAP54XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c -#define OMAP54XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 -#define OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c -#define OMAP54XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 -#define OMAP54XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec -#define OMAP54XX_PM_L3INIT_USB_OTG_SS_WKDEP_OFFSET 0x00f0 -#define OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET 0x00f4 - -/* PRM.CUSTEFUSE_PRM register offsets */ -#define OMAP54XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000 -#define OMAP54XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004 -#define OMAP54XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024 - -/* PRM.WKUPAON_PRM register offsets */ -#define OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0024 -#define OMAP54XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x002c -#define OMAP54XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x0030 -#define OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0034 -#define OMAP54XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0038 -#define OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x003c -#define OMAP54XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x0040 -#define OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0044 -#define OMAP54XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0048 -#define OMAP54XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x004c -#define OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0054 -#define OMAP54XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0064 -#define OMAP54XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0078 -#define OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x007c - -/* PRM.WKUPAON_CM register offsets */ -#define OMAP54XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000 -#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020 -#define OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0020) -#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028 -#define OMAP54XX_CM_WKUPAON_WD_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0028) -#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030 -#define OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0030) -#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038 -#define OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0038) -#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040 -#define OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0040) -#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048 -#define OMAP54XX_CM_WKUPAON_TIMER12_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0048) -#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050 -#define OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0050) -#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060 -#define OMAP54XX_CM_WKUPAON_SAR_RAM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0060) -#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078 -#define OMAP54XX_CM_WKUPAON_KBD_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0078) -#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090 -#define OMAP54XX_CM_WKUPAON_SCRM_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0090) -#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098 -#define OMAP54XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_WKUPAON_CM_INST, 0x0098) - -/* PRM.EMU_PRM register offsets */ -#define OMAP54XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000 -#define OMAP54XX_PM_EMU_PWRSTST_OFFSET 0x0004 -#define OMAP54XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 - -/* PRM.EMU_CM register offsets */ -#define OMAP54XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000 -#define OMAP54XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008 -#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0020 -#define OMAP54XX_CM_EMU_DEBUGSS_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0020) -#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x0028 -#define OMAP54XX_CM_EMU_MPU_EMU_DBG_CLKCTRL OMAP54XX_PRM_REGADDR(OMAP54XX_PRM_EMU_CM_INST, 0x0028) - /* PRM.DEVICE_PRM register offsets */ -#define OMAP54XX_PRM_RSTCTRL_OFFSET 0x0000 -#define OMAP54XX_PRM_RSTST_OFFSET 0x0004 -#define OMAP54XX_PRM_RSTTIME_OFFSET 0x0008 -#define OMAP54XX_PRM_CLKREQCTRL_OFFSET 0x000c -#define OMAP54XX_PRM_VOLTCTRL_OFFSET 0x0010 -#define OMAP54XX_PRM_PWRREQCTRL_OFFSET 0x0014 -#define OMAP54XX_PRM_PSCON_COUNT_OFFSET 0x0018 -#define OMAP54XX_PRM_IO_COUNT_OFFSET 0x001c -#define OMAP54XX_PRM_IO_PMCTRL_OFFSET 0x0020 -#define OMAP54XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 -#define OMAP54XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 -#define OMAP54XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c -#define OMAP54XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030 #define OMAP54XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 #define OMAP54XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 #define OMAP54XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c -#define OMAP54XX_PRM_VP_CORE_CONFIG_OFFSET 0x0040 -#define OMAP54XX_PRM_VP_CORE_STATUS_OFFSET 0x0044 -#define OMAP54XX_PRM_VP_CORE_VLIMITTO_OFFSET 0x0048 -#define OMAP54XX_PRM_VP_CORE_VOLTAGE_OFFSET 0x004c -#define OMAP54XX_PRM_VP_CORE_VSTEPMAX_OFFSET 0x0050 -#define OMAP54XX_PRM_VP_CORE_VSTEPMIN_OFFSET 0x0054 -#define OMAP54XX_PRM_VP_MPU_CONFIG_OFFSET 0x0058 -#define OMAP54XX_PRM_VP_MPU_STATUS_OFFSET 0x005c -#define OMAP54XX_PRM_VP_MPU_VLIMITTO_OFFSET 0x0060 -#define OMAP54XX_PRM_VP_MPU_VOLTAGE_OFFSET 0x0064 -#define OMAP54XX_PRM_VP_MPU_VSTEPMAX_OFFSET 0x0068 -#define OMAP54XX_PRM_VP_MPU_VSTEPMIN_OFFSET 0x006c -#define OMAP54XX_PRM_VP_MM_CONFIG_OFFSET 0x0070 -#define OMAP54XX_PRM_VP_MM_STATUS_OFFSET 0x0074 -#define OMAP54XX_PRM_VP_MM_VLIMITTO_OFFSET 0x0078 -#define OMAP54XX_PRM_VP_MM_VOLTAGE_OFFSET 0x007c -#define OMAP54XX_PRM_VP_MM_VSTEPMAX_OFFSET 0x0080 -#define OMAP54XX_PRM_VP_MM_VSTEPMIN_OFFSET 0x0084 -#define OMAP54XX_PRM_VC_SMPS_CORE_CONFIG_OFFSET 0x0088 -#define OMAP54XX_PRM_VC_SMPS_MM_CONFIG_OFFSET 0x008c -#define OMAP54XX_PRM_VC_SMPS_MPU_CONFIG_OFFSET 0x0090 -#define OMAP54XX_PRM_VC_VAL_CMD_VDD_CORE_L_OFFSET 0x0094 -#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MM_L_OFFSET 0x0098 -#define OMAP54XX_PRM_VC_VAL_CMD_VDD_MPU_L_OFFSET 0x009c -#define OMAP54XX_PRM_VC_VAL_BYPASS_OFFSET 0x00a0 -#define OMAP54XX_PRM_VC_CORE_ERRST_OFFSET 0x00a4 -#define OMAP54XX_PRM_VC_MM_ERRST_OFFSET 0x00a8 -#define OMAP54XX_PRM_VC_MPU_ERRST_OFFSET 0x00ac -#define OMAP54XX_PRM_VC_BYPASS_ERRST_OFFSET 0x00b0 -#define OMAP54XX_PRM_VC_CFG_I2C_MODE_OFFSET 0x00b4 -#define OMAP54XX_PRM_VC_CFG_I2C_CLK_OFFSET 0x00b8 -#define OMAP54XX_PRM_SRAM_COUNT_OFFSET 0x00bc -#define OMAP54XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0 -#define OMAP54XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4 -#define OMAP54XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8 -#define OMAP54XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc -#define OMAP54XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0 -#define OMAP54XX_PRM_SLDO_MM_SETUP_OFFSET 0x00d4 -#define OMAP54XX_PRM_SLDO_MM_CTRL_OFFSET 0x00d8 -#define OMAP54XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc -#define OMAP54XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0 -#define OMAP54XX_PRM_ABBLDO_MM_SETUP_OFFSET 0x00e4 -#define OMAP54XX_PRM_ABBLDO_MM_CTRL_OFFSET 0x00e8 -#define OMAP54XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec -#define OMAP54XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0 -#define OMAP54XX_PRM_PHASE1_CNDP_OFFSET 0x00f4 -#define OMAP54XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8 -#define OMAP54XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc -#define OMAP54XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100 -#define OMAP54XX_PRM_VOLTST_MPU_OFFSET 0x0110 -#define OMAP54XX_PRM_VOLTST_MM_OFFSET 0x0114 #endif diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h index e5aee0409eae..0ad1deba319f 100644 --- a/arch/arm/mach-omap2/prm7xx.h +++ b/arch/arm/mach-omap2/prm7xx.h @@ -56,625 +56,12 @@ #define DRA7XX_PRM_RTC_INST 0x1c60 #define DRA7XX_PRM_VPE_INST 0x1c80 #define DRA7XX_PRM_DEVICE_INST 0x1d00 -#define DRA7XX_PRM_INSTR_INST 0x1f00 /* PRM clockdomain register offsets (from instance start) */ #define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000 #define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000 -/* PRM */ - -/* PRM.OCP_SOCKET_PRM register offsets */ -#define DRA7XX_REVISION_PRM_OFFSET 0x0000 -#define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010 -#define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014 -#define DRA7XX_PRM_IRQENABLE_MPU_OFFSET 0x0018 -#define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c -#define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET 0x0020 -#define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET 0x0028 -#define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET 0x0030 -#define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET 0x0038 -#define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040 -#define DRA7XX_CM_PRM_PROFILING_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_OCP_SOCKET_INST, 0x0040) -#define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET 0x0044 -#define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET 0x0048 -#define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET 0x004c -#define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET 0x0050 -#define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET 0x0054 -#define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET 0x0058 -#define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET 0x005c -#define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET 0x0060 -#define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET 0x0064 -#define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET 0x0068 -#define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET 0x006c -#define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET 0x0070 -#define DRA7XX_PRM_DEBUG_CFG1_OFFSET 0x00e4 -#define DRA7XX_PRM_DEBUG_CFG2_OFFSET 0x00e8 -#define DRA7XX_PRM_DEBUG_CFG3_OFFSET 0x00ec -#define DRA7XX_PRM_DEBUG_OUT_OFFSET 0x00f4 - /* PRM.CKGEN_PRM register offsets */ -#define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET 0x0000 -#define DRA7XX_CM_CLKSEL_SYSCLK1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000) -#define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008 -#define DRA7XX_CM_CLKSEL_WKUPAON DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008) -#define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c -#define DRA7XX_CM_CLKSEL_ABE_PLL_REF DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c) -#define DRA7XX_CM_CLKSEL_SYS_OFFSET 0x0010 #define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010) -#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET 0x0014 -#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014) -#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET 0x0018 -#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018) -#define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET 0x001c -#define DRA7XX_CM_CLKSEL_ABE_24M DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c) -#define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET 0x0020 -#define DRA7XX_CM_CLKSEL_ABE_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020) -#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET 0x0024 -#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024) -#define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET 0x0028 -#define DRA7XX_CM_CLKSEL_HDMI_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028) -#define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET 0x002c -#define DRA7XX_CM_CLKSEL_MCASP_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c) -#define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET 0x0030 -#define DRA7XX_CM_CLKSEL_MLBP_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030) -#define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET 0x0034 -#define DRA7XX_CM_CLKSEL_MLB_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034) -#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET 0x0038 -#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038) -#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET 0x0040 -#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040) -#define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET 0x0044 -#define DRA7XX_CM_CLKSEL_TIMER_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044) -#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET 0x0048 -#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048) -#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET 0x004c -#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c) -#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET 0x0050 -#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050) -#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET 0x0054 -#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054) -#define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET 0x0058 -#define DRA7XX_CM_CLKSEL_CLKOUTMUX0 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058) -#define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET 0x005c -#define DRA7XX_CM_CLKSEL_CLKOUTMUX1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c) -#define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET 0x0060 -#define DRA7XX_CM_CLKSEL_CLKOUTMUX2 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060) -#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET 0x0064 -#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064) -#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET 0x0068 -#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068) -#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET 0x006c -#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c) -#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET 0x0070 -#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070) -#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET 0x0074 -#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074) -#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET 0x0078 -#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078) -#define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET 0x0080 -#define DRA7XX_CM_CLKSEL_EVE_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080) -#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET 0x0084 -#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084) -#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET 0x0088 -#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088) -#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET 0x008c -#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c) -#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET 0x0090 -#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090) -#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET 0x0094 -#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094) -#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET 0x0098 -#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098) -#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET 0x009c -#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c) -#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET 0x00a0 -#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0) -#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET 0x00a4 -#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4) -#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET 0x00a8 -#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8) -#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET 0x00ac -#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac) -#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET 0x00b0 -#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0) -#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET 0x00b4 -#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4) -#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET 0x00b8 -#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8) -#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET 0x00bc -#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc) -#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET 0x00c0 -#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0) -#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET 0x00c4 -#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4) -#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET 0x00c8 -#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8) -#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET 0x00cc -#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc) -#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET 0x00d0 -#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0) -#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET 0x00d4 -#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4) -#define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET 0x00d8 -#define DRA7XX_CM_CLKSEL_ABE_LP_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8) -#define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET 0x00dc -#define DRA7XX_CM_CLKSEL_ADC_GFCLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc) -#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET 0x00e0 -#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0) - -/* PRM.MPU_PRM register offsets */ -#define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_MPU_PWRSTST_OFFSET 0x0004 -#define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024 - -/* PRM.DSP1_PRM register offsets */ -#define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_DSP1_PWRSTST_OFFSET 0x0004 -#define DRA7XX_RM_DSP1_RSTCTRL_OFFSET 0x0010 -#define DRA7XX_RM_DSP1_RSTST_OFFSET 0x0014 -#define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET 0x0024 - -/* PRM.IPU_PRM register offsets */ -#define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_IPU_PWRSTST_OFFSET 0x0004 -#define DRA7XX_RM_IPU1_RSTCTRL_OFFSET 0x0010 -#define DRA7XX_RM_IPU1_RSTST_OFFSET 0x0014 -#define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET 0x0024 -#define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET 0x0050 -#define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET 0x0054 -#define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET 0x0058 -#define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET 0x005c -#define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET 0x0060 -#define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET 0x0064 -#define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET 0x0068 -#define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET 0x006c -#define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET 0x0070 -#define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET 0x0074 -#define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET 0x0078 -#define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET 0x007c -#define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET 0x0080 -#define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET 0x0084 - -/* PRM.COREAON_PRM register offsets */ -#define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0000 -#define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x0004 -#define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0010 -#define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x0014 -#define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET 0x0030 -#define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET 0x0034 -#define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET 0x0040 -#define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET 0x0044 -#define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET 0x0050 -#define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET 0x0054 -#define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET 0x0084 -#define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET 0x0094 -#define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET 0x00a4 -#define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET 0x00b4 - -/* PRM.CORE_PRM register offsets */ -#define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_CORE_PWRSTST_OFFSET 0x0004 -#define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024 -#define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET 0x002c -#define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET 0x0034 -#define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET 0x0050 -#define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET 0x0054 -#define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET 0x0058 -#define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET 0x005c -#define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET 0x0060 -#define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET 0x0064 -#define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET 0x006c -#define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET 0x0070 -#define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET 0x0074 -#define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET 0x0078 -#define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET 0x007c -#define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET 0x0080 -#define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET 0x0084 -#define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET 0x008c -#define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET 0x0094 -#define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET 0x009c -#define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET 0x00a4 -#define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET 0x00ac -#define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET 0x00b4 -#define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET 0x00bc -#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET 0x00c4 -#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET 0x00cc -#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET 0x00d4 -#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET 0x00dc -#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET 0x00f4 -#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET 0x00fc -#define DRA7XX_RM_IPU2_RSTCTRL_OFFSET 0x0210 -#define DRA7XX_RM_IPU2_RSTST_OFFSET 0x0214 -#define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET 0x0224 -#define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324 -#define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424 -#define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c -#define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434 -#define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c -#define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444 -#define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET 0x0524 -#define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624 -#define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c -#define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET 0x0634 -#define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c -#define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644 -#define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET 0x064c -#define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET 0x0654 -#define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET 0x065c -#define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET 0x0664 -#define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET 0x066c -#define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET 0x0674 -#define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET 0x067c -#define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET 0x0684 -#define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET 0x068c -#define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET 0x0694 -#define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET 0x069c -#define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET 0x06a4 -#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET 0x06ac -#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET 0x06b4 -#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET 0x06bc -#define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET 0x06c4 -#define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET 0x0724 -#define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c -#define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744 - -/* PRM.IVA_PRM register offsets */ -#define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_IVA_PWRSTST_OFFSET 0x0004 -#define DRA7XX_RM_IVA_RSTCTRL_OFFSET 0x0010 -#define DRA7XX_RM_IVA_RSTST_OFFSET 0x0014 -#define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024 -#define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c - -/* PRM.CAM_PRM register offsets */ -#define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_CAM_PWRSTST_OFFSET 0x0004 -#define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET 0x0020 -#define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET 0x0024 -#define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET 0x0028 -#define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET 0x002c -#define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET 0x0030 -#define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET 0x0034 -#define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET 0x003c -#define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET 0x0044 -#define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET 0x004c - -/* PRM.DSS_PRM register offsets */ -#define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_DSS_PWRSTST_OFFSET 0x0004 -#define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020 -#define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024 -#define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET 0x0028 -#define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034 -#define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET 0x003c - -/* PRM.GPU_PRM register offsets */ -#define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_GPU_PWRSTST_OFFSET 0x0004 -#define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024 - -/* PRM.L3INIT_PRM register offsets */ -#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004 -#define DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET 0x0010 -#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028 -#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c -#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030 -#define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034 -#define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET 0x0040 -#define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET 0x0044 -#define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET 0x0048 -#define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET 0x004c -#define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET 0x0050 -#define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET 0x0054 -#define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET 0x005c -#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c -#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088 -#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c -#define DRA7XX_PM_L3INIT_PCIESS1_WKDEP_OFFSET 0x00b0 -#define DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET 0x00b4 -#define DRA7XX_PM_L3INIT_PCIESS2_WKDEP_OFFSET 0x00b8 -#define DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET 0x00bc -#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4 -#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4 -#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec -#define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET 0x00f0 -#define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET 0x00f4 - -/* PRM.L4PER_PRM register offsets */ -#define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_L4PER_PWRSTST_OFFSET 0x0004 -#define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET 0x000c -#define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET 0x0014 -#define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET 0x001c -#define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET 0x0024 -#define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0028 -#define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x002c -#define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0030 -#define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0034 -#define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0038 -#define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x003c -#define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0040 -#define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0044 -#define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0048 -#define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x004c -#define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0050 -#define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0054 -#define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c -#define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060 -#define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064 -#define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068 -#define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c -#define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070 -#define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074 -#define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078 -#define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c -#define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080 -#define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084 -#define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c -#define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET 0x0094 -#define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET 0x009c -#define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0 -#define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4 -#define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8 -#define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac -#define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0 -#define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4 -#define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8 -#define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc -#define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET 0x00c0 -#define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET 0x00c4 -#define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET 0x00c8 -#define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET 0x00cc -#define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET 0x00d0 -#define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET 0x00d4 -#define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET 0x00d8 -#define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET 0x00dc -#define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0 -#define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4 -#define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8 -#define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc -#define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100 -#define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104 -#define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108 -#define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c -#define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0110 -#define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0114 -#define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0118 -#define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x011c -#define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0120 -#define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0124 -#define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0128 -#define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x012c -#define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET 0x0130 -#define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET 0x0134 -#define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET 0x0138 -#define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET 0x013c -#define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0140 -#define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144 -#define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0148 -#define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c -#define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0150 -#define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154 -#define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0158 -#define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c -#define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET 0x0160 -#define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET 0x0164 -#define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET 0x0168 -#define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET 0x016c -#define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0170 -#define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0174 -#define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET 0x0178 -#define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET 0x017c -#define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET 0x0180 -#define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET 0x0184 -#define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET 0x0188 -#define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET 0x018c -#define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET 0x0190 -#define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET 0x0194 -#define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET 0x0198 -#define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET 0x019c -#define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4 -#define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac -#define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4 -#define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x01bc -#define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4 -#define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc -#define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET 0x01d0 -#define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET 0x01d4 -#define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x01dc -#define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET 0x01e0 -#define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET 0x01e4 -#define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET 0x01e8 -#define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET 0x01ec -#define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET 0x01f0 -#define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET 0x01f4 -#define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET 0x01fc - -/* PRM.CUSTEFUSE_PRM register offsets */ -#define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004 -#define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024 - -/* PRM.WKUPAON_PRM register offsets */ -#define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0000 -#define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET 0x0004 -#define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x0008 -#define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x000c -#define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0010 -#define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0014 -#define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x0018 -#define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x001c -#define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0020 -#define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0024 -#define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x0028 -#define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0030 -#define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0040 -#define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0054 -#define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x0058 -#define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET 0x005c -#define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET 0x0060 -#define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET 0x0064 -#define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET 0x0068 -#define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET 0x007c -#define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET 0x0080 -#define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET 0x0090 -#define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET 0x0098 -#define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET 0x00a0 -#define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET 0x00a8 -#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET 0x00b0 -#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET 0x00b8 - -/* PRM.WKUPAON_CM register offsets */ -#define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020 -#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0020) -#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028 -#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0028) -#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030 -#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0030) -#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038 -#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0038) -#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040 -#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0040) -#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048 -#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0048) -#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050 -#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0050) -#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060 -#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0060) -#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078 -#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0078) -#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET 0x0080 -#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0080) -#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET 0x0088 -#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0088) -#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090 -#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0090) -#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098 -#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0098) -#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET 0x00a0 -#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00a0) -#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET 0x00b0 -#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b0) -#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET 0x00b8 -#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b8) -#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET 0x00c0 -#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c0) -#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET 0x00c8 -#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c8) -#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET 0x00d0 -#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d0) -#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET 0x00d8 -#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d8) - -/* PRM.EMU_PRM register offsets */ -#define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_EMU_PWRSTST_OFFSET 0x0004 -#define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024 - -/* PRM.EMU_CM register offsets */ -#define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000 -#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0004 -#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x0004) -#define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008 -#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x000c -#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x000c) - -/* PRM.DSP2_PRM register offsets */ -#define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_DSP2_PWRSTST_OFFSET 0x0004 -#define DRA7XX_RM_DSP2_RSTCTRL_OFFSET 0x0010 -#define DRA7XX_RM_DSP2_RSTST_OFFSET 0x0014 -#define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET 0x0024 - -/* PRM.EVE1_PRM register offsets */ -#define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_EVE1_PWRSTST_OFFSET 0x0004 -#define DRA7XX_RM_EVE1_RSTCTRL_OFFSET 0x0010 -#define DRA7XX_RM_EVE1_RSTST_OFFSET 0x0014 -#define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET 0x0020 -#define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET 0x0024 - -/* PRM.EVE2_PRM register offsets */ -#define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_EVE2_PWRSTST_OFFSET 0x0004 -#define DRA7XX_RM_EVE2_RSTCTRL_OFFSET 0x0010 -#define DRA7XX_RM_EVE2_RSTST_OFFSET 0x0014 -#define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET 0x0020 -#define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET 0x0024 - -/* PRM.EVE3_PRM register offsets */ -#define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_EVE3_PWRSTST_OFFSET 0x0004 -#define DRA7XX_RM_EVE3_RSTCTRL_OFFSET 0x0010 -#define DRA7XX_RM_EVE3_RSTST_OFFSET 0x0014 -#define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET 0x0020 -#define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET 0x0024 - -/* PRM.EVE4_PRM register offsets */ -#define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_EVE4_PWRSTST_OFFSET 0x0004 -#define DRA7XX_RM_EVE4_RSTCTRL_OFFSET 0x0010 -#define DRA7XX_RM_EVE4_RSTST_OFFSET 0x0014 -#define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET 0x0020 -#define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET 0x0024 - -/* PRM.RTC_PRM register offsets */ -#define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET 0x0000 -#define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET 0x0004 - -/* PRM.VPE_PRM register offsets */ -#define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET 0x0000 -#define DRA7XX_PM_VPE_PWRSTST_OFFSET 0x0004 -#define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET 0x0020 -#define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET 0x0024 - -/* PRM.DEVICE_PRM register offsets */ -#define DRA7XX_PRM_RSTCTRL_OFFSET 0x0000 -#define DRA7XX_PRM_RSTST_OFFSET 0x0004 -#define DRA7XX_PRM_RSTTIME_OFFSET 0x0008 -#define DRA7XX_PRM_CLKREQCTRL_OFFSET 0x000c -#define DRA7XX_PRM_VOLTCTRL_OFFSET 0x0010 -#define DRA7XX_PRM_PWRREQCTRL_OFFSET 0x0014 -#define DRA7XX_PRM_PSCON_COUNT_OFFSET 0x0018 -#define DRA7XX_PRM_IO_COUNT_OFFSET 0x001c -#define DRA7XX_PRM_IO_PMCTRL_OFFSET 0x0020 -#define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024 -#define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028 -#define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c -#define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030 -#define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034 -#define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038 -#define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c -#define DRA7XX_PRM_SRAM_COUNT_OFFSET 0x00bc -#define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0 -#define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4 -#define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8 -#define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc -#define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0 -#define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET 0x00d4 -#define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET 0x00d8 -#define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc -#define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0 -#define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET 0x00e4 -#define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET 0x00e8 -#define DRA7XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec -#define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0 -#define DRA7XX_PRM_PHASE1_CNDP_OFFSET 0x00f4 -#define DRA7XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8 -#define DRA7XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc -#define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100 -#define DRA7XX_PRM_VOLTST_MPU_OFFSET 0x0110 -#define DRA7XX_PRM_VOLTST_MM_OFFSET 0x0114 -#define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET 0x0118 -#define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET 0x011c -#define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET 0x0120 -#define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET 0x0124 -#define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET 0x0128 -#define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET 0x012c -#define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET 0x0130 -#define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET 0x0134 #endif diff --git a/arch/arm/mach-omap2/scrm44xx.h b/arch/arm/mach-omap2/scrm44xx.h index 3f530b89e4c9..2e861aa951f0 100644 --- a/arch/arm/mach-omap2/scrm44xx.h +++ b/arch/arm/mach-omap2/scrm44xx.h @@ -22,72 +22,7 @@ OMAP2_L4_IO_ADDRESS(OMAP4_SCRM_BASE + (reg)) /* Registers offset */ -#define OMAP4_SCRM_REVISION_SCRM_OFFSET 0x0000 -#define OMAP4_SCRM_REVISION_SCRM OMAP44XX_SCRM_REGADDR(0x0000) -#define OMAP4_SCRM_CLKSETUPTIME_OFFSET 0x0100 #define OMAP4_SCRM_CLKSETUPTIME OMAP44XX_SCRM_REGADDR(0x0100) -#define OMAP4_SCRM_PMICSETUPTIME_OFFSET 0x0104 -#define OMAP4_SCRM_PMICSETUPTIME OMAP44XX_SCRM_REGADDR(0x0104) -#define OMAP4_SCRM_ALTCLKSRC_OFFSET 0x0110 -#define OMAP4_SCRM_ALTCLKSRC OMAP44XX_SCRM_REGADDR(0x0110) -#define OMAP4_SCRM_MODEMCLKM_OFFSET 0x0118 -#define OMAP4_SCRM_MODEMCLKM OMAP44XX_SCRM_REGADDR(0x0118) -#define OMAP4_SCRM_D2DCLKM_OFFSET 0x011c -#define OMAP4_SCRM_D2DCLKM OMAP44XX_SCRM_REGADDR(0x011c) -#define OMAP4_SCRM_EXTCLKREQ_OFFSET 0x0200 -#define OMAP4_SCRM_EXTCLKREQ OMAP44XX_SCRM_REGADDR(0x0200) -#define OMAP4_SCRM_ACCCLKREQ_OFFSET 0x0204 -#define OMAP4_SCRM_ACCCLKREQ OMAP44XX_SCRM_REGADDR(0x0204) -#define OMAP4_SCRM_PWRREQ_OFFSET 0x0208 -#define OMAP4_SCRM_PWRREQ OMAP44XX_SCRM_REGADDR(0x0208) -#define OMAP4_SCRM_AUXCLKREQ0_OFFSET 0x0210 -#define OMAP4_SCRM_AUXCLKREQ0 OMAP44XX_SCRM_REGADDR(0x0210) -#define OMAP4_SCRM_AUXCLKREQ1_OFFSET 0x0214 -#define OMAP4_SCRM_AUXCLKREQ1 OMAP44XX_SCRM_REGADDR(0x0214) -#define OMAP4_SCRM_AUXCLKREQ2_OFFSET 0x0218 -#define OMAP4_SCRM_AUXCLKREQ2 OMAP44XX_SCRM_REGADDR(0x0218) -#define OMAP4_SCRM_AUXCLKREQ3_OFFSET 0x021c -#define OMAP4_SCRM_AUXCLKREQ3 OMAP44XX_SCRM_REGADDR(0x021c) -#define OMAP4_SCRM_AUXCLKREQ4_OFFSET 0x0220 -#define OMAP4_SCRM_AUXCLKREQ4 OMAP44XX_SCRM_REGADDR(0x0220) -#define OMAP4_SCRM_AUXCLKREQ5_OFFSET 0x0224 -#define OMAP4_SCRM_AUXCLKREQ5 OMAP44XX_SCRM_REGADDR(0x0224) -#define OMAP4_SCRM_D2DCLKREQ_OFFSET 0x0234 -#define OMAP4_SCRM_D2DCLKREQ OMAP44XX_SCRM_REGADDR(0x0234) -#define OMAP4_SCRM_AUXCLK0_OFFSET 0x0310 -#define OMAP4_SCRM_AUXCLK0 OMAP44XX_SCRM_REGADDR(0x0310) -#define OMAP4_SCRM_AUXCLK1_OFFSET 0x0314 -#define OMAP4_SCRM_AUXCLK1 OMAP44XX_SCRM_REGADDR(0x0314) -#define OMAP4_SCRM_AUXCLK2_OFFSET 0x0318 -#define OMAP4_SCRM_AUXCLK2 OMAP44XX_SCRM_REGADDR(0x0318) -#define OMAP4_SCRM_AUXCLK3_OFFSET 0x031c -#define OMAP4_SCRM_AUXCLK3 OMAP44XX_SCRM_REGADDR(0x031c) -#define OMAP4_SCRM_AUXCLK4_OFFSET 0x0320 -#define OMAP4_SCRM_AUXCLK4 OMAP44XX_SCRM_REGADDR(0x0320) -#define OMAP4_SCRM_AUXCLK5_OFFSET 0x0324 -#define OMAP4_SCRM_AUXCLK5 OMAP44XX_SCRM_REGADDR(0x0324) -#define OMAP4_SCRM_RSTTIME_OFFSET 0x0400 -#define OMAP4_SCRM_RSTTIME OMAP44XX_SCRM_REGADDR(0x0400) -#define OMAP4_SCRM_MODEMRSTCTRL_OFFSET 0x0418 -#define OMAP4_SCRM_MODEMRSTCTRL OMAP44XX_SCRM_REGADDR(0x0418) -#define OMAP4_SCRM_D2DRSTCTRL_OFFSET 0x041c -#define OMAP4_SCRM_D2DRSTCTRL OMAP44XX_SCRM_REGADDR(0x041c) -#define OMAP4_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420 -#define OMAP4_SCRM_EXTPWRONRSTCTRL OMAP44XX_SCRM_REGADDR(0x0420) -#define OMAP4_SCRM_EXTWARMRSTST_OFFSET 0x0510 -#define OMAP4_SCRM_EXTWARMRSTST OMAP44XX_SCRM_REGADDR(0x0510) -#define OMAP4_SCRM_APEWARMRSTST_OFFSET 0x0514 -#define OMAP4_SCRM_APEWARMRSTST OMAP44XX_SCRM_REGADDR(0x0514) -#define OMAP4_SCRM_MODEMWARMRSTST_OFFSET 0x0518 -#define OMAP4_SCRM_MODEMWARMRSTST OMAP44XX_SCRM_REGADDR(0x0518) -#define OMAP4_SCRM_D2DWARMRSTST_OFFSET 0x051c -#define OMAP4_SCRM_D2DWARMRSTST OMAP44XX_SCRM_REGADDR(0x051c) - -/* Registers shifts and masks */ - -/* REVISION_SCRM */ -#define OMAP4_REV_SHIFT 0 -#define OMAP4_REV_MASK (0xff << 0) /* CLKSETUPTIME */ #define OMAP4_DOWNTIME_SHIFT 16 @@ -95,80 +30,4 @@ #define OMAP4_SETUPTIME_SHIFT 0 #define OMAP4_SETUPTIME_MASK (0xfff << 0) -/* PMICSETUPTIME */ -#define OMAP4_WAKEUPTIME_SHIFT 16 -#define OMAP4_WAKEUPTIME_MASK (0x3f << 16) -#define OMAP4_SLEEPTIME_SHIFT 0 -#define OMAP4_SLEEPTIME_MASK (0x3f << 0) - -/* ALTCLKSRC */ -#define OMAP4_ENABLE_EXT_SHIFT 3 -#define OMAP4_ENABLE_EXT_MASK (1 << 3) -#define OMAP4_ENABLE_INT_SHIFT 2 -#define OMAP4_ENABLE_INT_MASK (1 << 2) -#define OMAP4_ALTCLKSRC_MODE_SHIFT 0 -#define OMAP4_ALTCLKSRC_MODE_MASK (0x3 << 0) - -/* MODEMCLKM */ -#define OMAP4_CLK_32KHZ_SHIFT 0 -#define OMAP4_CLK_32KHZ_MASK (1 << 0) - -/* D2DCLKM */ -#define OMAP4_SYSCLK_SHIFT 1 -#define OMAP4_SYSCLK_MASK (1 << 1) - -/* EXTCLKREQ */ -#define OMAP4_POLARITY_SHIFT 0 -#define OMAP4_POLARITY_MASK (1 << 0) - -/* AUXCLKREQ0 */ -#define OMAP4_MAPPING_SHIFT 2 -#define OMAP4_MAPPING_MASK (0x7 << 2) -#define OMAP4_MAPPING_WIDTH 3 -#define OMAP4_ACCURACY_SHIFT 1 -#define OMAP4_ACCURACY_MASK (1 << 1) - -/* AUXCLK0 */ -#define OMAP4_CLKDIV_SHIFT 16 -#define OMAP4_CLKDIV_MASK (0xf << 16) -#define OMAP4_CLKDIV_WIDTH 4 -#define OMAP4_DISABLECLK_SHIFT 9 -#define OMAP4_DISABLECLK_MASK (1 << 9) -#define OMAP4_ENABLE_SHIFT 8 -#define OMAP4_ENABLE_MASK (1 << 8) -#define OMAP4_SRCSELECT_SHIFT 1 -#define OMAP4_SRCSELECT_MASK (0x3 << 1) - -/* RSTTIME */ -#define OMAP4_RSTTIME_SHIFT 0 -#define OMAP4_RSTTIME_MASK (0xf << 0) - -/* MODEMRSTCTRL */ -#define OMAP4_WARMRST_SHIFT 1 -#define OMAP4_WARMRST_MASK (1 << 1) -#define OMAP4_COLDRST_SHIFT 0 -#define OMAP4_COLDRST_MASK (1 << 0) - -/* EXTPWRONRSTCTRL */ -#define OMAP4_PWRONRST_SHIFT 1 -#define OMAP4_PWRONRST_MASK (1 << 1) -#define OMAP4_ENABLE_EXTPWRONRSTCTRL_SHIFT 0 -#define OMAP4_ENABLE_EXTPWRONRSTCTRL_MASK (1 << 0) - -/* EXTWARMRSTST */ -#define OMAP4_EXTWARMRSTST_SHIFT 0 -#define OMAP4_EXTWARMRSTST_MASK (1 << 0) - -/* APEWARMRSTST */ -#define OMAP4_APEWARMRSTST_SHIFT 1 -#define OMAP4_APEWARMRSTST_MASK (1 << 1) - -/* MODEMWARMRSTST */ -#define OMAP4_MODEMWARMRSTST_SHIFT 2 -#define OMAP4_MODEMWARMRSTST_MASK (1 << 2) - -/* D2DWARMRSTST */ -#define OMAP4_D2DWARMRSTST_SHIFT 3 -#define OMAP4_D2DWARMRSTST_MASK (1 << 3) - #endif diff --git a/arch/arm/mach-omap2/scrm54xx.h b/arch/arm/mach-omap2/scrm54xx.h deleted file mode 100644 index cb6f3e6a7095..000000000000 --- a/arch/arm/mach-omap2/scrm54xx.h +++ /dev/null @@ -1,228 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * OMAP54XX SCRM registers and bitfields - * - * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com - * - * Benoit Cousson (b-cousson@ti.com) - * - * This file is automatically generated from the OMAP hardware databases. - * We respectfully ask that any modifications to this file be coordinated - * with the public linux-omap@vger.kernel.org mailing list and the - * authors above to ensure that the autogeneration scripts are kept - * up-to-date with the file contents. - */ - -#ifndef __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H -#define __ARCH_ARM_MACH_OMAP2_SCRM_54XX_H - -#define OMAP5_SCRM_BASE 0x4ae0a000 - -#define OMAP54XX_SCRM_REGADDR(reg) \ - OMAP2_L4_IO_ADDRESS(OMAP5_SCRM_BASE + (reg)) - -/* SCRM */ - -/* SCRM.SCRM register offsets */ -#define OMAP5_SCRM_REVISION_SCRM_OFFSET 0x0000 -#define OMAP5_SCRM_REVISION_SCRM OMAP54XX_SCRM_REGADDR(0x0000) -#define OMAP5_SCRM_CLKSETUPTIME_OFFSET 0x0100 -#define OMAP5_SCRM_CLKSETUPTIME OMAP54XX_SCRM_REGADDR(0x0100) -#define OMAP5_SCRM_PMICSETUPTIME_OFFSET 0x0104 -#define OMAP5_SCRM_PMICSETUPTIME OMAP54XX_SCRM_REGADDR(0x0104) -#define OMAP5_SCRM_ALTCLKSRC_OFFSET 0x0110 -#define OMAP5_SCRM_ALTCLKSRC OMAP54XX_SCRM_REGADDR(0x0110) -#define OMAP5_SCRM_MODEMCLKM_OFFSET 0x0118 -#define OMAP5_SCRM_MODEMCLKM OMAP54XX_SCRM_REGADDR(0x0118) -#define OMAP5_SCRM_D2DCLKM_OFFSET 0x011c -#define OMAP5_SCRM_D2DCLKM OMAP54XX_SCRM_REGADDR(0x011c) -#define OMAP5_SCRM_EXTCLKREQ_OFFSET 0x0200 -#define OMAP5_SCRM_EXTCLKREQ OMAP54XX_SCRM_REGADDR(0x0200) -#define OMAP5_SCRM_ACCCLKREQ_OFFSET 0x0204 -#define OMAP5_SCRM_ACCCLKREQ OMAP54XX_SCRM_REGADDR(0x0204) -#define OMAP5_SCRM_PWRREQ_OFFSET 0x0208 -#define OMAP5_SCRM_PWRREQ OMAP54XX_SCRM_REGADDR(0x0208) -#define OMAP5_SCRM_AUXCLKREQ0_OFFSET 0x0210 -#define OMAP5_SCRM_AUXCLKREQ0 OMAP54XX_SCRM_REGADDR(0x0210) -#define OMAP5_SCRM_AUXCLKREQ1_OFFSET 0x0214 -#define OMAP5_SCRM_AUXCLKREQ1 OMAP54XX_SCRM_REGADDR(0x0214) -#define OMAP5_SCRM_AUXCLKREQ2_OFFSET 0x0218 -#define OMAP5_SCRM_AUXCLKREQ2 OMAP54XX_SCRM_REGADDR(0x0218) -#define OMAP5_SCRM_AUXCLKREQ3_OFFSET 0x021c -#define OMAP5_SCRM_AUXCLKREQ3 OMAP54XX_SCRM_REGADDR(0x021c) -#define OMAP5_SCRM_AUXCLKREQ4_OFFSET 0x0220 -#define OMAP5_SCRM_AUXCLKREQ4 OMAP54XX_SCRM_REGADDR(0x0220) -#define OMAP5_SCRM_AUXCLKREQ5_OFFSET 0x0224 -#define OMAP5_SCRM_AUXCLKREQ5 OMAP54XX_SCRM_REGADDR(0x0224) -#define OMAP5_SCRM_D2DCLKREQ_OFFSET 0x0234 -#define OMAP5_SCRM_D2DCLKREQ OMAP54XX_SCRM_REGADDR(0x0234) -#define OMAP5_SCRM_AUXCLK0_OFFSET 0x0310 -#define OMAP5_SCRM_AUXCLK0 OMAP54XX_SCRM_REGADDR(0x0310) -#define OMAP5_SCRM_AUXCLK1_OFFSET 0x0314 -#define OMAP5_SCRM_AUXCLK1 OMAP54XX_SCRM_REGADDR(0x0314) -#define OMAP5_SCRM_AUXCLK2_OFFSET 0x0318 -#define OMAP5_SCRM_AUXCLK2 OMAP54XX_SCRM_REGADDR(0x0318) -#define OMAP5_SCRM_AUXCLK3_OFFSET 0x031c -#define OMAP5_SCRM_AUXCLK3 OMAP54XX_SCRM_REGADDR(0x031c) -#define OMAP5_SCRM_AUXCLK4_OFFSET 0x0320 -#define OMAP5_SCRM_AUXCLK4 OMAP54XX_SCRM_REGADDR(0x0320) -#define OMAP5_SCRM_AUXCLK5_OFFSET 0x0324 -#define OMAP5_SCRM_AUXCLK5 OMAP54XX_SCRM_REGADDR(0x0324) -#define OMAP5_SCRM_RSTTIME_OFFSET 0x0400 -#define OMAP5_SCRM_RSTTIME OMAP54XX_SCRM_REGADDR(0x0400) -#define OMAP5_SCRM_MODEMRSTCTRL_OFFSET 0x0418 -#define OMAP5_SCRM_MODEMRSTCTRL OMAP54XX_SCRM_REGADDR(0x0418) -#define OMAP5_SCRM_D2DRSTCTRL_OFFSET 0x041c -#define OMAP5_SCRM_D2DRSTCTRL OMAP54XX_SCRM_REGADDR(0x041c) -#define OMAP5_SCRM_EXTPWRONRSTCTRL_OFFSET 0x0420 -#define OMAP5_SCRM_EXTPWRONRSTCTRL OMAP54XX_SCRM_REGADDR(0x0420) -#define OMAP5_SCRM_EXTWARMRSTST_OFFSET 0x0510 -#define OMAP5_SCRM_EXTWARMRSTST OMAP54XX_SCRM_REGADDR(0x0510) -#define OMAP5_SCRM_APEWARMRSTST_OFFSET 0x0514 -#define OMAP5_SCRM_APEWARMRSTST OMAP54XX_SCRM_REGADDR(0x0514) -#define OMAP5_SCRM_MODEMWARMRSTST_OFFSET 0x0518 -#define OMAP5_SCRM_MODEMWARMRSTST OMAP54XX_SCRM_REGADDR(0x0518) -#define OMAP5_SCRM_D2DWARMRSTST_OFFSET 0x051c -#define OMAP5_SCRM_D2DWARMRSTST OMAP54XX_SCRM_REGADDR(0x051c) - -/* - * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, - * AUXCLKREQ5, D2DCLKREQ - */ -#define OMAP5_ACCURACY_SHIFT 1 -#define OMAP5_ACCURACY_WIDTH 0x1 -#define OMAP5_ACCURACY_MASK (1 << 1) - -/* Used by APEWARMRSTST */ -#define OMAP5_APEWARMRSTST_SHIFT 1 -#define OMAP5_APEWARMRSTST_WIDTH 0x1 -#define OMAP5_APEWARMRSTST_MASK (1 << 1) - -/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ -#define OMAP5_CLKDIV_SHIFT 16 -#define OMAP5_CLKDIV_WIDTH 0x4 -#define OMAP5_CLKDIV_MASK (0xf << 16) - -/* Used by D2DCLKM, MODEMCLKM */ -#define OMAP5_CLK_32KHZ_SHIFT 0 -#define OMAP5_CLK_32KHZ_WIDTH 0x1 -#define OMAP5_CLK_32KHZ_MASK (1 << 0) - -/* Used by D2DRSTCTRL, MODEMRSTCTRL */ -#define OMAP5_COLDRST_SHIFT 0 -#define OMAP5_COLDRST_WIDTH 0x1 -#define OMAP5_COLDRST_MASK (1 << 0) - -/* Used by D2DWARMRSTST */ -#define OMAP5_D2DWARMRSTST_SHIFT 3 -#define OMAP5_D2DWARMRSTST_WIDTH 0x1 -#define OMAP5_D2DWARMRSTST_MASK (1 << 3) - -/* Used by AUXCLK0 */ -#define OMAP5_DISABLECLK_SHIFT 9 -#define OMAP5_DISABLECLK_WIDTH 0x1 -#define OMAP5_DISABLECLK_MASK (1 << 9) - -/* Used by CLKSETUPTIME */ -#define OMAP5_DOWNTIME_SHIFT 16 -#define OMAP5_DOWNTIME_WIDTH 0x6 -#define OMAP5_DOWNTIME_MASK (0x3f << 16) - -/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ -#define OMAP5_ENABLE_SHIFT 8 -#define OMAP5_ENABLE_WIDTH 0x1 -#define OMAP5_ENABLE_MASK (1 << 8) - -/* Renamed from ENABLE Used by EXTPWRONRSTCTRL */ -#define OMAP5_ENABLE_0_0_SHIFT 0 -#define OMAP5_ENABLE_0_0_WIDTH 0x1 -#define OMAP5_ENABLE_0_0_MASK (1 << 0) - -/* Used by ALTCLKSRC */ -#define OMAP5_ENABLE_EXT_SHIFT 3 -#define OMAP5_ENABLE_EXT_WIDTH 0x1 -#define OMAP5_ENABLE_EXT_MASK (1 << 3) - -/* Used by ALTCLKSRC */ -#define OMAP5_ENABLE_INT_SHIFT 2 -#define OMAP5_ENABLE_INT_WIDTH 0x1 -#define OMAP5_ENABLE_INT_MASK (1 << 2) - -/* Used by EXTWARMRSTST */ -#define OMAP5_EXTWARMRSTST_SHIFT 0 -#define OMAP5_EXTWARMRSTST_WIDTH 0x1 -#define OMAP5_EXTWARMRSTST_MASK (1 << 0) - -/* - * Used by AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, - * AUXCLKREQ5 - */ -#define OMAP5_MAPPING_SHIFT 2 -#define OMAP5_MAPPING_WIDTH 0x3 -#define OMAP5_MAPPING_MASK (0x7 << 2) - -/* Used by ALTCLKSRC */ -#define OMAP5_MODE_SHIFT 0 -#define OMAP5_MODE_WIDTH 0x2 -#define OMAP5_MODE_MASK (0x3 << 0) - -/* Used by MODEMWARMRSTST */ -#define OMAP5_MODEMWARMRSTST_SHIFT 2 -#define OMAP5_MODEMWARMRSTST_WIDTH 0x1 -#define OMAP5_MODEMWARMRSTST_MASK (1 << 2) - -/* - * Used by ACCCLKREQ, AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5, - * AUXCLKREQ0, AUXCLKREQ1, AUXCLKREQ2, AUXCLKREQ3, AUXCLKREQ4, AUXCLKREQ5, - * D2DCLKREQ, EXTCLKREQ, PWRREQ - */ -#define OMAP5_POLARITY_SHIFT 0 -#define OMAP5_POLARITY_WIDTH 0x1 -#define OMAP5_POLARITY_MASK (1 << 0) - -/* Used by EXTPWRONRSTCTRL */ -#define OMAP5_PWRONRST_SHIFT 1 -#define OMAP5_PWRONRST_WIDTH 0x1 -#define OMAP5_PWRONRST_MASK (1 << 1) - -/* Used by REVISION_SCRM */ -#define OMAP5_REV_SHIFT 0 -#define OMAP5_REV_WIDTH 0x8 -#define OMAP5_REV_MASK (0xff << 0) - -/* Used by RSTTIME */ -#define OMAP5_RSTTIME_SHIFT 0 -#define OMAP5_RSTTIME_WIDTH 0x4 -#define OMAP5_RSTTIME_MASK (0xf << 0) - -/* Used by CLKSETUPTIME */ -#define OMAP5_SETUPTIME_SHIFT 0 -#define OMAP5_SETUPTIME_WIDTH 0xc -#define OMAP5_SETUPTIME_MASK (0xfff << 0) - -/* Used by PMICSETUPTIME */ -#define OMAP5_SLEEPTIME_SHIFT 0 -#define OMAP5_SLEEPTIME_WIDTH 0x6 -#define OMAP5_SLEEPTIME_MASK (0x3f << 0) - -/* Used by AUXCLK0, AUXCLK1, AUXCLK2, AUXCLK3, AUXCLK4, AUXCLK5 */ -#define OMAP5_SRCSELECT_SHIFT 1 -#define OMAP5_SRCSELECT_WIDTH 0x2 -#define OMAP5_SRCSELECT_MASK (0x3 << 1) - -/* Used by D2DCLKM */ -#define OMAP5_SYSCLK_SHIFT 1 -#define OMAP5_SYSCLK_WIDTH 0x1 -#define OMAP5_SYSCLK_MASK (1 << 1) - -/* Used by PMICSETUPTIME */ -#define OMAP5_WAKEUPTIME_SHIFT 16 -#define OMAP5_WAKEUPTIME_WIDTH 0x6 -#define OMAP5_WAKEUPTIME_MASK (0x3f << 16) - -/* Used by D2DRSTCTRL, MODEMRSTCTRL */ -#define OMAP5_WARMRST_SHIFT 1 -#define OMAP5_WARMRST_WIDTH 0x1 -#define OMAP5_WARMRST_MASK (1 << 1) - -#endif diff --git a/arch/arm/mach-s3c/irq-s3c24xx.c b/arch/arm/mach-s3c/irq-s3c24xx.c index 45dfd546e6fa..3776d5206f9b 100644 --- a/arch/arm/mach-s3c/irq-s3c24xx.c +++ b/arch/arm/mach-s3c/irq-s3c24xx.c @@ -361,11 +361,25 @@ static inline int s3c24xx_handle_intc(struct s3c_irq_intc *intc, static asmlinkage void __exception_irq_entry s3c24xx_handle_irq(struct pt_regs *regs) { do { - if (likely(s3c_intc[0])) - if (s3c24xx_handle_intc(s3c_intc[0], regs, 0)) - continue; + /* + * For platform based machines, neither ERR nor NULL can happen here. + * The s3c24xx_handle_irq() will be set as IRQ handler iff this succeeds: + * + * s3c_intc[0] = s3c24xx_init_intc() + * + * If this fails, the next calls to s3c24xx_init_intc() won't be executed. + * + * For DT machine, s3c_init_intc_of() could set the IRQ handler without + * setting s3c_intc[0] only if it was called with num_ctrl=0. There is no + * such code path, so again the s3c_intc[0] will have a valid pointer if + * set_handle_irq() is called. + * + * Therefore in s3c24xx_handle_irq(), the s3c_intc[0] is always something. + */ + if (s3c24xx_handle_intc(s3c_intc[0], regs, 0)) + continue; - if (s3c_intc[2]) + if (!IS_ERR_OR_NULL(s3c_intc[2])) if (s3c24xx_handle_intc(s3c_intc[2], regs, 64)) continue; diff --git a/arch/arm/mach-s3c/mach-mini6410.c b/arch/arm/mach-s3c/mach-mini6410.c index 741fa1f09694..c14c2e27127b 100644 --- a/arch/arm/mach-s3c/mach-mini6410.c +++ b/arch/arm/mach-s3c/mach-mini6410.c @@ -262,7 +262,7 @@ static char mini6410_features_str[12] __initdata = "0"; static int __init mini6410_features_setup(char *str) { if (str) - strlcpy(mini6410_features_str, str, + strscpy(mini6410_features_str, str, sizeof(mini6410_features_str)); return 1; } diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index 57699bd8f107..98145031586f 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -48,6 +48,14 @@ config MACH_STM32MP157 select ARM_ERRATA_814220 default y +config MACH_STM32MP13 + bool "STMicroelectronics STM32MP13x" + select ARM_ERRATA_814220 + default y + help + Support for STM32MP13 SoCs: + STM32MP131, STM32MP133, STM32MP135 + endif # ARMv7-A endif diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c index a766310d8dca..2ccaa11aaa56 100644 --- a/arch/arm/mach-stm32/board-dt.c +++ b/arch/arm/mach-stm32/board-dt.c @@ -18,6 +18,9 @@ static const char *const stm32_compat[] __initconst = { "st,stm32f769", "st,stm32h743", "st,stm32h750", + "st,stm32mp131", + "st,stm32mp133", + "st,stm32mp135", "st,stm32mp157", NULL }; diff --git a/arch/arm/mach-sunxi/platsmp.c b/arch/arm/mach-sunxi/platsmp.c index bdde9ef3aaa9..052097e78e6e 100644 --- a/arch/arm/mach-sunxi/platsmp.c +++ b/arch/arm/mach-sunxi/platsmp.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * SMP support for Allwinner SoCs * @@ -8,9 +9,6 @@ * Based on code * Copyright (C) 2012-2013 Allwinner Ltd. * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include <linux/delay.h> diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c index 19635721013d..e1b7945aac99 100644 --- a/arch/arm/mach-sunxi/sunxi.c +++ b/arch/arm/mach-sunxi/sunxi.c @@ -1,3 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Device Tree support for Allwinner A1X SoCs * @@ -5,9 +6,6 @@ * * Maxime Ripard <maxime.ripard@free-electrons.com> * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include <linux/clocksource.h> |