diff options
| author | Stijn Tintel | 2022-04-03 05:59:49 +0300 |
|---|---|---|
| committer | Thomas Bogendoerfer | 2022-04-26 15:12:03 +0200 |
| commit | 407710a3b52c32db6f212727f06620f1c38ed1d2 (patch) | |
| tree | 42065ff6cef4a4d24cd2ef203bab9676c81b18c7 | |
| parent | 4107fa700f314592850e2c64608f6ede4c077476 (diff) | |
MIPS: Octeon: fix CN6640 hang on XAUI init
Some CN66XX series Octeon II chips seem to hang if a reset is issued on
XAUI initialization. Avoid the hang by disabling the reset.
Tested on SNIC10E.
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
| -rw-r--r-- | arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c index fea71a85bb29..a92632223497 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-xaui.c @@ -156,8 +156,9 @@ int __cvmx_helper_xaui_enable(int interface) xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface)); xauiCtl.s.lo_pwr = 0; - /* Issuing a reset here seems to hang some CN68XX chips. */ - if (!OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) && + /* Issuing a reset here seems to hang some CN66XX/CN68XX chips. */ + if (!OCTEON_IS_MODEL(OCTEON_CN66XX) && + !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X) && !OCTEON_IS_MODEL(OCTEON_CN68XX_PASS2_X)) xauiCtl.s.reset = 1; |