diff options
| author | David Daney | 2013-07-29 15:07:03 -0700 |
|---|---|---|
| committer | Ralf Baechle | 2013-08-26 15:31:53 +0200 |
| commit | 4723b20a381ae488d845f3e041ef1dd71c6f40f8 (patch) | |
| tree | ae8040eee924f541d84148ce2f931df5bba8b7a6 | |
| parent | 4122af0ab02a4b394e4703a3ac557d556701f4d9 (diff) | |
MIPS: Generate OCTEON3 TLB handlers with the same features as OCTEON2.
OCTEON2 need the same code.
Signed-off-by: David Daney <david.daney@cavium.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5637/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/mm/tlbex.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 556cb4815770..821b45175dc1 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -85,6 +85,7 @@ static int use_bbit_insns(void) case CPU_CAVIUM_OCTEON: case CPU_CAVIUM_OCTEON_PLUS: case CPU_CAVIUM_OCTEON2: + case CPU_CAVIUM_OCTEON3: return 1; default: return 0; @@ -95,6 +96,7 @@ static int use_lwx_insns(void) { switch (current_cpu_type()) { case CPU_CAVIUM_OCTEON2: + case CPU_CAVIUM_OCTEON3: return 1; default: return 0; |