diff options
| author | Ramalingam C | 2021-11-16 09:48:17 -0800 |
|---|---|---|
| committer | Matt Roper | 2021-12-02 21:38:38 -0800 |
| commit | 4b19f6b728c7ae0cc285d2012d5aa1ab99be9b39 (patch) | |
| tree | 485c9b6df34a97e4ee4193df660e791173b4539e | |
| parent | 34734ab72763d51c6b809ee80ceb04a161a37dd1 (diff) | |
drm/i915/dg2: Add Wa_16013000631
Invalidate IC cache through pipe control command as part of the ctx
restore flow through indirect ctx pointer.
v2:
- Move pipe control from xcs indirect context to the rcs indirect
context. We'll eventually need this on the CCS engines too, but
support for those hasn't landed yet.
Cc: Chris Wilson <chris.p.wilson@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211116174818.2128062-5-matthew.d.roper@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_lrc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 56156cf18c41..b3489599e4de 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -1167,6 +1167,11 @@ gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs) cs = gen12_emit_cmd_buf_wa(ce, cs); cs = gen12_emit_restore_scratch(ce, cs); + /* Wa_16013000631:dg2 */ + if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_B0, STEP_C0) || + IS_DG2_G11(ce->engine->i915)) + cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0); + return cs; } |