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| author | Chris Packham | 2019-07-12 05:46:54 +0100 |
|---|---|---|
| committer | Russell King | 2019-08-29 07:58:01 +0100 |
| commit | 4bf4770db4f0dbf495ca6236644abb413501f6e0 (patch) | |
| tree | c3abcf96ce1f79eef8ae8f7c371bad57c3d8d6ff | |
| parent | fd3bbde717b00a2db75d0c93264f412c1176008f (diff) | |
ARM: 8889/1: dt-bindings: document marvell,ecc-enable binding
Add documentation for the marvell,ecc-enable properties which can be
used to enable ECC on the Marvell aurora cache.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
| -rw-r--r-- | Documentation/devicetree/bindings/arm/l2c2x0.yaml | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.yaml b/Documentation/devicetree/bindings/arm/l2c2x0.yaml index bfc5c185561c..913a8cd8b2c0 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.yaml +++ b/Documentation/devicetree/bindings/arm/l2c2x0.yaml @@ -176,6 +176,10 @@ properties: description: disable parity checking on the L2 cache (L220 or PL310). type: boolean + marvell,ecc-enable: + description: enable ECC protection on the L2 cache + type: boolean + arm,outer-sync-disable: description: disable the outer sync operation on the L2 cache. Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that |