diff options
| author | Jordan Niethe | 2020-08-27 14:05:56 +1000 |
|---|---|---|
| committer | Michael Ellerman | 2020-09-08 22:57:11 +1000 |
| commit | 51a1588154cb1ddc4fe8fa786324dca398f1a458 (patch) | |
| tree | bc5dddd6d29f4a292be91638f537d55d47e17ef8 | |
| parent | 0fb4871bcc8997acbb8edf14b301fc150101d6c0 (diff) | |
powerpc: Update documentation of ISA versions for Power10
Update the CPU to ISA Version Mapping document to include Power10 and
ISA v3.1.
Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
[mpe: Make sure ISA reference is unique]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20200827040556.1783-1-jniethe5@gmail.com
| -rw-r--r-- | Documentation/powerpc/isa-versions.rst | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/powerpc/isa-versions.rst b/Documentation/powerpc/isa-versions.rst index a363d8c1603c..dfcb1097dce4 100644 --- a/Documentation/powerpc/isa-versions.rst +++ b/Documentation/powerpc/isa-versions.rst @@ -7,6 +7,7 @@ Mapping of some CPU versions to relevant ISA versions. ========= ==================================================================== CPU Architecture version ========= ==================================================================== +Power10 Power ISA v3.1 Power9 Power ISA v3.0B Power8 Power ISA v2.07 Power7 Power ISA v2.06 @@ -32,6 +33,7 @@ Key Features ========== ================== CPU VMX (aka. Altivec) ========== ================== +Power10 Yes Power9 Yes Power8 Yes Power7 Yes @@ -47,6 +49,7 @@ PPC970 Yes ========== ==== CPU VSX ========== ==== +Power10 Yes Power9 Yes Power8 Yes Power7 Yes @@ -62,6 +65,7 @@ PPC970 No ========== ==================================== CPU Transactional Memory ========== ==================================== +Power10 No (* see Power ISA v3.1, "Appendix A. Notes on the Removal of Transactional Memory from the Architecture") Power9 Yes (* see transactional_memory.txt) Power8 Yes Power7 No |