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authorChristian Marangi2022-07-07 03:09:37 +0200
committerBjorn Andersson2022-07-16 21:43:51 -0500
commit5c47a46d5e942ea6b041c8b7727b201817c1ff76 (patch)
treef2c75d433fbee73430d5d74869727972d2b554d5
parentd883a12a547b6d42e795ff3b5ac87cfd013b5423 (diff)
ARM: dts: qcom: ipq8064: add specific dtsi with smb208 rpm regulators
Add specific ipq8064 dtsi with smb208 rpm regulators. Qcom advise to use this configuration but it's not mandatory and OEM can decide to implement their own regulators. smb208 regulators are used to scale CPU voltage, L2 cache voltage and Ubi32 cores. There regulators are controlled by rpm and to correctly works gsbi4-i2c require to be NEVER disabled or rpm will reject any regulator change request. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Tested-by: Jonathan McDowell <noodles@earth.li> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220707010943.20857-4-ansuelsmth@gmail.com
-rw-r--r--arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi37
1 files changed, 37 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
new file mode 100644
index 000000000000..ac9c44f0c164
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq8064-smb208.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include "qcom-ipq8064.dtsi"
+
+&rpm {
+ smb208_regulators: regulators {
+ compatible = "qcom,rpm-smb208-regulators";
+
+ smb208_s1a: s1a {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s1b: s1b {
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1150000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2a: s2a {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1250000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+
+ smb208_s2b: s2b {
+ regulator-min-microvolt = < 800000>;
+ regulator-max-microvolt = <1250000>;
+
+ qcom,switch-mode-frequency = <1200000>;
+ };
+ };
+};