diff options
| author | Zhang Le | 2009-04-15 17:01:52 +0800 |
|---|---|---|
| committer | Ralf Baechle | 2009-05-14 13:50:26 +0100 |
| commit | 5d57c31e5790d44905af0459a21086dbad167d26 (patch) | |
| tree | d834becb495bdba4d59d5ae46e96f566586b54cd | |
| parent | 6cec2a0ac57d2ebef495a46d7866ae86e8d0e508 (diff) | |
MIPS: Loongson 2 needs no hazard barriers.
Quoting from Loongson2FUserGuide.pdf:
5.22.1 Hazards
The processor detects most of the pipeline hazards in hardware, including
CP0 hazards and load hazards. No NOP instructions are required to correct
instruction sequences.
Signed-off-by: Zhang Le <r0bertz@gentoo.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/include/asm/hazards.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index a12d971db4f9..0eaf77ffbc4f 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -138,8 +138,9 @@ do { \ __instruction_hazard(); \ } while (0) -#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ - defined(CONFIG_CPU_R5500) || defined(CONFIG_MACH_ALCHEMY) +#elif defined(CONFIG_MACH_ALCHEMY) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ + defined(CONFIG_CPU_LOONGSON2) || defined(CONFIG_CPU_R10000) || \ + defined(CONFIG_CPU_R5500) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. |