diff options
| author | Atsushi Nemoto | 2007-05-21 23:45:38 +0900 |
|---|---|---|
| committer | Ralf Baechle | 2007-06-06 19:34:33 +0100 |
| commit | 6ba07e590d1f841a5d0539978399b852a015ab53 (patch) | |
| tree | 69817e59dc8d83947aace1f2ade39b0c636ff323 | |
| parent | 490dcc4d309141b622107ad5ad82674a01e089bc (diff) | |
[MIPS] Fix warning by moving do_default_vi into CONFIG_CPU_MIPSR2_SRS
This fixes the warning:
arch/mips/kernel/traps.c:931: warning: 'do_default_vi' defined but not used
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/kernel/traps.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 200de027f354..3f58b6ac1358 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -927,12 +927,6 @@ asmlinkage void do_reserved(struct pt_regs *regs) (regs->cp0_cause & 0x7f) >> 2); } -static asmlinkage void do_default_vi(void) -{ - show_regs(get_irq_regs()); - panic("Caught unexpected vectored interrupt."); -} - /* * Some MIPS CPUs can enable/disable for cache parity detection, but do * it different ways. @@ -1128,6 +1122,12 @@ void mips_srs_free(int set) clear_bit(set, &sr->sr_allocated); } +static asmlinkage void do_default_vi(void) +{ + show_regs(get_irq_regs()); + panic("Caught unexpected vectored interrupt."); +} + static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) { unsigned long handler; |