diff options
| author | Grygorii Strashko | 2020-03-03 18:00:26 +0200 |
|---|---|---|
| committer | Kishon Vijay Abraham I | 2020-03-20 19:34:29 +0530 |
| commit | 74e29703a78c120cd129e2b49ac8213713d2648c (patch) | |
| tree | 6131881cbf838c435afc68ada92626b83b06fbce | |
| parent | 6076967a500c4c6dad19d10d71863db1590a35ed (diff) | |
dt-bindings: phy: ti: gmii-sel: add support for am654x/j721e soc
TI AM654x/J721E SoCs have the same PHY interface selection mechanism for
CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields
placement is different.
This patch adds corresponding compatible strings to enable support for TI
AM654x/J721E SoCs.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
| -rw-r--r-- | Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt b/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt index 50ce9ae0f7a5..83b78c1c0644 100644 --- a/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt +++ b/Documentation/devicetree/bindings/phy/ti-phy-gmii-sel.txt @@ -40,6 +40,7 @@ Required properties: "ti,dra7xx-phy-gmii-sel" for dra7xx/am57xx platform "ti,am43xx-phy-gmii-sel" for am43xx platform "ti,dm814-phy-gmii-sel" for dm814x platform + "ti,am654-phy-gmii-sel" for AM654x/J721E platform - reg : Address and length of the register set for the device - #phy-cells : must be 2. cell 1 - CPSW port number (starting from 1) |