diff options
| author | Vladimir Oltean | 2020-03-19 23:16:48 +0200 |
|---|---|---|
| committer | David S. Miller | 2020-03-23 20:52:27 -0700 |
| commit | 7b005a1742be4608480d9d151aec42170a06cbee (patch) | |
| tree | ad1fc3c639ee965ba6ebc6117fc73152e5b8b5a5 | |
| parent | da206d65f2b293274f8082a26da4e43a1610da54 (diff) | |
net: phy: mscc: configure both RX and TX internal delays for RGMII
The driver appears to be secretly enabling the RX clock skew
irrespective of PHY interface type, which is generally considered a big
no-no.
Make them configurable instead, and add TX internal delays when
necessary too.
While at it, configure a more canonical clock skew of 2.0 nanoseconds
than the current default of 1.1 ns.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
| -rw-r--r-- | drivers/net/phy/mscc/mscc.h | 2 | ||||
| -rw-r--r-- | drivers/net/phy/mscc/mscc_main.c | 16 |
2 files changed, 15 insertions, 3 deletions
diff --git a/drivers/net/phy/mscc/mscc.h b/drivers/net/phy/mscc/mscc.h index 99e2d20596ad..0f04afd81816 100644 --- a/drivers/net/phy/mscc/mscc.h +++ b/drivers/net/phy/mscc/mscc.h @@ -178,6 +178,8 @@ enum rgmii_clock_delay { #define MSCC_PHY_RGMII_CNTL 20 #define RGMII_RX_CLK_DELAY_MASK 0x0070 #define RGMII_RX_CLK_DELAY_POS 4 +#define RGMII_TX_CLK_DELAY_MASK 0x0007 +#define RGMII_TX_CLK_DELAY_POS 0 #define MSCC_PHY_WOL_LOWER_MAC_ADDR 21 #define MSCC_PHY_WOL_MID_MAC_ADDR 22 diff --git a/drivers/net/phy/mscc/mscc_main.c b/drivers/net/phy/mscc/mscc_main.c index c1aaf9f8b243..c162fbaec1d7 100644 --- a/drivers/net/phy/mscc/mscc_main.c +++ b/drivers/net/phy/mscc/mscc_main.c @@ -522,16 +522,26 @@ out_unlock: static int vsc85xx_default_config(struct phy_device *phydev) { + u16 reg_val = 0; int rc; - u16 reg_val; phydev->mdix_ctrl = ETH_TP_MDI_AUTO; + + if (!phy_interface_mode_is_rgmii(phydev->interface)) + return 0; + mutex_lock(&phydev->lock); - reg_val = RGMII_CLK_DELAY_1_1_NS << RGMII_RX_CLK_DELAY_POS; + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + reg_val |= RGMII_CLK_DELAY_2_0_NS << RGMII_RX_CLK_DELAY_POS; + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + reg_val |= RGMII_CLK_DELAY_2_0_NS << RGMII_TX_CLK_DELAY_POS; rc = phy_modify_paged(phydev, MSCC_PHY_PAGE_EXTENDED_2, - MSCC_PHY_RGMII_CNTL, RGMII_RX_CLK_DELAY_MASK, + MSCC_PHY_RGMII_CNTL, + RGMII_RX_CLK_DELAY_MASK | RGMII_TX_CLK_DELAY_MASK, reg_val); mutex_unlock(&phydev->lock); |