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authorNeil Armstrong2019-06-20 16:46:55 +0200
committerThierry Reding2019-06-25 14:57:44 +0200
commit9bce02ef0dfa4d3816756a85c9f25dd63592d65f (patch)
tree6a96fe322cb6591b19ea91e9b1f41985b2739d07
parent1cdb44135dd87cd4eac77b06c075486881f04767 (diff)
pwm: meson: Fix the G12A AO clock parents order
The Amlogic G12A and G12B Documentation is wrong, the AO xtal and clk81 clock source order is reversed, and validated when adding DVFS support by using the PWM AO D output to control the CPU supply voltage. The vendor tree also uses the reversed xtal and clk81 order at [1]. [1] https://github.com/hardkernel/linux/blob/odroidn2-4.9.y/drivers/amlogic/pwm/pwm_meson.c#L462 Fixes: f41efceb46e6 ("pwm: meson: Add clock source configuration for Meson G12A") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
-rw-r--r--drivers/pwm/pwm-meson.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index 5fef7e925282..32baf6f6a895 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -383,8 +383,17 @@ static const struct meson_pwm_data pwm_axg_ao_data = {
.num_parents = ARRAY_SIZE(pwm_axg_ao_parent_names),
};
+static const char * const pwm_g12a_ao_ab_parent_names[] = {
+ "xtal", "aoclk81", "fclk_div4", "fclk_div5"
+};
+
+static const struct meson_pwm_data pwm_g12a_ao_ab_data = {
+ .parent_names = pwm_g12a_ao_ab_parent_names,
+ .num_parents = ARRAY_SIZE(pwm_g12a_ao_ab_parent_names),
+};
+
static const char * const pwm_g12a_ao_cd_parent_names[] = {
- "aoclk81", "xtal",
+ "xtal", "aoclk81",
};
static const struct meson_pwm_data pwm_g12a_ao_cd_data = {
@@ -428,7 +437,7 @@ static const struct of_device_id meson_pwm_matches[] = {
},
{
.compatible = "amlogic,meson-g12a-ao-pwm-ab",
- .data = &pwm_axg_ao_data
+ .data = &pwm_g12a_ao_ab_data
},
{
.compatible = "amlogic,meson-g12a-ao-pwm-cd",