diff options
| author | Guo Ren | 2021-09-24 15:33:38 +0800 |
|---|---|---|
| committer | Guo Ren | 2021-10-16 07:20:12 +0800 |
| commit | af89ebaa64de726ca0a39bbb0bf0c81a1f43ad50 (patch) | |
| tree | 42259e29611ea2266daeedb158aae45af783ba85 | |
| parent | fbd63c08cdcca5fb1315aca3172b3c9c272cfb4f (diff) | |
csky: Fixup regs.sr broken in ptrace
gpr_get() return the entire pt_regs (include sr) to userspace, if we
don't restore the C bit in gpr_set, it may break the ALU result in
that context. So the C flag bit is part of gpr context, that's why
riscv totally remove the C bit in the ISA. That makes sr reg clear
from userspace to supervisor privilege.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Cc: stable@vger.kernel.org
| -rw-r--r-- | arch/csky/kernel/ptrace.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/csky/kernel/ptrace.c b/arch/csky/kernel/ptrace.c index 0105ac81b432..1a5f54e0d272 100644 --- a/arch/csky/kernel/ptrace.c +++ b/arch/csky/kernel/ptrace.c @@ -99,7 +99,8 @@ static int gpr_set(struct task_struct *target, if (ret) return ret; - regs.sr = task_pt_regs(target)->sr; + /* BIT(0) of regs.sr is Condition Code/Carry bit */ + regs.sr = (regs.sr & BIT(0)) | (task_pt_regs(target)->sr & ~BIT(0)); #ifdef CONFIG_CPU_HAS_HILO regs.dcsr = task_pt_regs(target)->dcsr; #endif |