diff options
| author | Vidya Sagar | 2022-10-25 23:55:08 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman | 2022-12-31 13:31:52 +0100 |
| commit | b2429741cb42a4598538b361388eb5deb9bca427 (patch) | |
| tree | 9fbc4294981fda67e71261d0076f9de91f249ab1 | |
| parent | 75a0e121937d4bcdc5c1ddd6fb3d0c8ea1ad56be (diff) | |
arm64: tegra: Fix non-prefetchable aperture of PCIe C3 controller
[ Upstream commit 47a2f35d9ea76d92aa2385671f527b75aa9dfe45 ]
Fix the starting address of the non-prefetchable aperture of PCIe C3
controller.
Fixes: ec142c44b026 ("arm64: tegra: Add P2U and PCIe controller nodes to Tegra234 DT")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
| -rw-r--r-- | arch/arm64/boot/dts/nvidia/tegra234.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi index 9b43a0b0d775..dfe2cf2f4b21 100644 --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi @@ -2178,7 +2178,7 @@ bus-range = <0x0 0xff>; ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */ - <0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ + <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */ <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */ interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>, |