diff options
| author | Krzysztof Adamski | 2016-02-09 15:58:49 +0100 |
|---|---|---|
| committer | Linus Walleij | 2016-02-11 14:30:29 +0100 |
| commit | be2d107f44339def4c2cfb876c7c001e4169e419 (patch) | |
| tree | 8c33a64a3a5df372f3c4c8b149ebcf02e5e73539 | |
| parent | ba83a11104ae7d156c73f4db288ec7a0b7edcdb5 (diff) | |
pinctrl: sunxi: Use pin number when calling sunxi_pmx_set
sunxi_pmx_set accepts pin number and then calculates offset by
subtracting pin_base from it. sunxi_pinctrl_gpio_get, on the other hand,
gets offset so we have to convert it to pin number so we won't get
negative value in sunxi_pmx_set.
This was only used on A10 so far, where there is only one GPIO chip with
pin_base set to 0 so it didn't matter. However H3 also requires this
workaround but have two pinmux sections, triggering problem for PL port.
Signed-off-by: Krzysztof Adamski <k@japko.eu>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| -rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sunxi.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index 7a2465f5e71e..96f64a104a62 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -459,15 +459,16 @@ static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset) u8 index = sunxi_data_offset(offset); u32 set_mux = pctl->desc->irq_read_needs_mux && test_bit(FLAG_USED_AS_IRQ, &chip->desc[offset].flags); + u32 pin = offset + chip->base; u32 val; if (set_mux) - sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_INPUT); + sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_INPUT); val = (readl(pctl->membase + reg) >> index) & DATA_PINS_MASK; if (set_mux) - sunxi_pmx_set(pctl->pctl_dev, offset, SUN4I_FUNC_IRQ); + sunxi_pmx_set(pctl->pctl_dev, pin, SUN4I_FUNC_IRQ); return !!val; } |