diff options
| author | Rodrigo Vivi | 2015-11-11 11:37:09 -0800 |
|---|---|---|
| committer | Daniel Vetter | 2015-11-18 16:01:39 +0100 |
| commit | bebbeaca841b999f90742a5f391d449ff37a7204 (patch) | |
| tree | fbd4430325c57fa6a73c053c2974483e271046e5 | |
| parent | 20bb97fe0ecc02f25666fc26f0ac79a6f1515a2b (diff) | |
drm/i915: PSR: Don't Skip aux handshake on DP_PSR_NO_TRAIN_ON_EXIT.
Since the beginning there is a confusion on the meaning of this bit.
A previous patch had identified this already and fixed it partially:
'commit 3301d409 ("drm/i915: PSR: Fix DP_PSR_NO_TRAIN_ON_EXIT logic")
DP_PSR_NO_TRAIN_ON_EXIT means the source doesn't need to do the
training, but it doesn't tell to avoid TP patterns or to skip
aux handshake.
This patch fixes the hard freeze reported.
Reference: https://bugs.freedesktop.org/show_bug.cgi?id=91436
Reference: https://bugs.freedesktop.org/show_bug.cgi?id=91437
Cc: Ivan Mitev <ivan.mitev@gmail.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_psr.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 715a48b95dc5..c4a63712c68e 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -287,7 +287,6 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp) send the minimal TP1 possible and skip TP2. */ val |= EDP_PSR_TP1_TIME_100us; val |= EDP_PSR_TP2_TP3_TIME_0us; - val |= EDP_PSR_SKIP_AUX_EXIT; /* Sink should be able to train with the 5 or 6 idle patterns */ idle_frames += 4; } |