diff options
| author | Keyon Jie | 2021-03-19 14:49:50 +0200 |
|---|---|---|
| committer | Mark Brown | 2021-03-22 12:32:23 +0000 |
| commit | bf939446c357242b3306e88c5f48976940d29679 (patch) | |
| tree | 62426012d179c1b974303f06525ce47af4360e2b | |
| parent | b951b51e2ca4d37dc9781e14d8a49d2f2b7e715b (diff) | |
ASoC: intel: sof_rt5682: use the topology mclk
We should use the topology configured mclk if it existed, which can make
sure we are aligned with the FW side about the mclk usage.
Signed-off-by: Keyon Jie <yang.jie@linux.intel.com>
Reviewed-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Reviewed-by: Daniel Baluta <daniel.baluta@gmail.com>
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Link: https://lore.kernel.org/r/20210319124950.3853994-2-kai.vehmanen@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | sound/soc/intel/boards/sof_rt5682.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/sound/soc/intel/boards/sof_rt5682.c b/sound/soc/intel/boards/sof_rt5682.c index f4b898c1719f..58548ea0d915 100644 --- a/sound/soc/intel/boards/sof_rt5682.c +++ b/sound/soc/intel/boards/sof_rt5682.c @@ -16,6 +16,7 @@ #include <sound/pcm.h> #include <sound/pcm_params.h> #include <sound/soc.h> +#include <sound/sof.h> #include <sound/rt5682.h> #include <sound/soc-acpi.h> #include "../../codecs/rt1015.h" @@ -268,10 +269,21 @@ static int sof_rt5682_hw_params(struct snd_pcm_substream *substream, } clk_id = RT5682_PLL1_S_MCLK; - if (sof_rt5682_quirk & SOF_RT5682_MCLK_24MHZ) + + /* get the tplg configured mclk. */ + clk_freq = sof_dai_get_mclk(rtd); + + /* mclk from the quirk is the first choice */ + if (sof_rt5682_quirk & SOF_RT5682_MCLK_24MHZ) { + if (clk_freq != 24000000) + dev_warn(rtd->dev, "configure wrong mclk in tplg, please use 24MHz.\n"); clk_freq = 24000000; - else + } else if (clk_freq == 0) { + /* use default mclk if not specified correct in topology */ clk_freq = 19200000; + } else if (clk_freq < 0) { + return clk_freq; + } } else { clk_id = RT5682_PLL1_S_BCLK1; clk_freq = params_rate(params) * 50; |