diff options
| author | Daniele Alessandrelli | 2020-11-26 11:51:47 +0000 |
|---|---|---|
| committer | Herbert Xu | 2020-12-11 21:12:04 +1100 |
| commit | c7e34aa31d6297a3a49a0c0142df858838d4b54f (patch) | |
| tree | eab1c38f3d20e4e11961d025a2f786d4ce414afb | |
| parent | 0464e0ef4f144bd5f2fa6ef6e06ab1e0ae4806f6 (diff) | |
dt-bindings: Add Keem Bay OCS AES bindings
Add device-tree bindings for Intel Keem Bay Offload and Crypto Subsystem
(OCS) AES crypto driver.
Signed-off-by: Daniele Alessandrelli <daniele.alessandrelli@intel.com>
Acked-by: Mark Gross <mgross@linux.intel.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
| -rw-r--r-- | Documentation/devicetree/bindings/crypto/intel,keembay-ocs-aes.yaml | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/crypto/intel,keembay-ocs-aes.yaml b/Documentation/devicetree/bindings/crypto/intel,keembay-ocs-aes.yaml new file mode 100644 index 000000000000..ee2c099981b2 --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/intel,keembay-ocs-aes.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/intel,keembay-ocs-aes.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay OCS AES Device Tree Bindings + +maintainers: + - Daniele Alessandrelli <daniele.alessandrelli@intel.com> + +description: + The Intel Keem Bay Offload and Crypto Subsystem (OCS) AES engine provides + hardware-accelerated AES/SM4 encryption/decryption. + +properties: + compatible: + const: intel,keembay-ocs-aes + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + crypto@30008000 { + compatible = "intel,keembay-ocs-aes"; + reg = <0x30008000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&scmi_clk 95>; + }; |