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authorShawn Guo2012-05-04 14:32:35 +0800
committerShawn Guo2012-05-12 13:32:19 +0800
commitce4c6f9b5987ac9402788c518bc5bd8b8572aa1e (patch)
treeb065be1ed1491eccc226ae9b0e000cfb203331ee
parent4052d45e800ce33e1993fb70604941547ed73d26 (diff)
ARM: mxs: add gpio support for device tree boot
It adds gpio support for device tree boot. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r--arch/arm/boot/dts/imx23.dtsi35
-rw-r--r--arch/arm/boot/dts/imx28.dtsi55
-rw-r--r--arch/arm/mach-mxs/mach-mxs.c12
3 files changed, 100 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index a85ef5514747..26220550f2f8 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -14,6 +14,12 @@
/ {
interrupt-parent = <&icoll>;
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ };
+
cpus {
cpu@0 {
compatible = "arm,arm926ejs";
@@ -74,9 +80,36 @@
pinctrl@80018000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,imx23-pinctrl";
+ compatible = "fsl,imx23-pinctrl", "simple-bus";
reg = <0x80018000 2000>;
+ gpio0: gpio@0 {
+ compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
+ interrupts = <16>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@1 {
+ compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
+ interrupts = <17>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2 {
+ compatible = "fsl,imx23-gpio", "fsl,mxs-gpio";
+ interrupts = <18>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
duart_pins_a: duart@0 {
reg = <0>;
fsl,pinmux-ids = <0x11a2 0x11b2>;
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index a17fbfcb2f83..1abd9b37691c 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -14,6 +14,14 @@
/ {
interrupt-parent = <&icoll>;
+ aliases {
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ gpio2 = &gpio2;
+ gpio3 = &gpio3;
+ gpio4 = &gpio4;
+ };
+
cpus {
cpu@0 {
compatible = "arm,arm926ejs";
@@ -97,9 +105,54 @@
pinctrl@80018000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "fsl,imx28-pinctrl";
+ compatible = "fsl,imx28-pinctrl", "simple-bus";
reg = <0x80018000 2000>;
+ gpio0: gpio@0 {
+ compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ interrupts = <127>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@1 {
+ compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ interrupts = <126>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio@2 {
+ compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ interrupts = <125>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio@3 {
+ compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ interrupts = <124>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio@4 {
+ compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
+ interrupts = <123>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
duart_pins_a: duart@0 {
reg = <0>;
fsl,pinmux-ids = <0x3102 0x3112>;
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index 182ea7529d28..8cac94b33020 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -30,8 +30,20 @@ static int __init mxs_icoll_add_irq_domain(struct device_node *np,
return 0;
}
+static int __init mxs_gpio_add_irq_domain(struct device_node *np,
+ struct device_node *interrupt_parent)
+{
+ static int gpio_irq_base = MXS_GPIO_IRQ_START;
+
+ irq_domain_add_legacy(np, 32, gpio_irq_base, 0, &irq_domain_simple_ops, NULL);
+ gpio_irq_base += 32;
+
+ return 0;
+}
+
static const struct of_device_id mxs_irq_match[] __initconst = {
{ .compatible = "fsl,mxs-icoll", .data = mxs_icoll_add_irq_domain, },
+ { .compatible = "fsl,mxs-gpio", .data = mxs_gpio_add_irq_domain, },
{ /* sentinel */ }
};