diff options
| author | Lars Povlsen | 2020-05-13 14:55:25 +0200 |
|---|---|---|
| committer | Linus Walleij | 2020-05-18 09:32:43 +0200 |
| commit | e695dea067fca398b7eb0f0977f4692986b483f7 (patch) | |
| tree | 7c2b5456c3c30f17c6386d6e58ff22575ea274b5 | |
| parent | 0b47afc65453a70bc521e251138418056f65793f (diff) | |
dt-bindings: pinctrl: ocelot: Add Sparx5 SoC support
This adds documentation for the "compatible" value designated for Sparx5
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Link: https://lore.kernel.org/r/20200513125532.24585-8-lars.povlsen@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| -rw-r--r-- | Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt index 32a8a8fa7805..00912449237b 100644 --- a/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt @@ -2,8 +2,8 @@ Microsemi Ocelot pin controller Device Tree Bindings ---------------------------------------------------- Required properties: - - compatible : Should be "mscc,ocelot-pinctrl" or - "mscc,jaguar2-pinctrl" + - compatible : Should be "mscc,ocelot-pinctrl", + "mscc,jaguar2-pinctrl" or "microchip,sparx5-pinctrl" - reg : Address and length of the register set for the device - gpio-controller : Indicates this device is a GPIO controller - #gpio-cells : Must be 2. |