diff options
| author | Rafał Miłecki | 2016-04-17 22:53:04 +0200 |
|---|---|---|
| committer | Boris Brezillon | 2016-05-05 23:52:05 +0200 |
| commit | ef296dc947f6a9300a7fb5b696d1e1f543479e18 (patch) | |
| tree | 169f8c7c00fe99a2e9103955eb44d779c97448b1 | |
| parent | e9d4faed71d5a63fa0ef8fcfef559f67f8b85a22 (diff) | |
mtd: nand: fsmc: validate ECC setup by checking algorithm directly
NAND core sets ECC algorithm in algo field now and it should be
preferred over the mode field. This also prepares driver for dropping
NAND_ECC_SOFT_BCH.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| -rw-r--r-- | drivers/mtd/nand/fsmc_nand.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/mtd/nand/fsmc_nand.c b/drivers/mtd/nand/fsmc_nand.c index 13720405ec81..0f8c63f85f86 100644 --- a/drivers/mtd/nand/fsmc_nand.c +++ b/drivers/mtd/nand/fsmc_nand.c @@ -958,9 +958,12 @@ static int __init fsmc_nand_probe(struct platform_device *pdev) nand->ecc.strength = 1; break; + case NAND_ECC_SOFT: case NAND_ECC_SOFT_BCH: - dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n"); - break; + if (nand->ecc.algo == NAND_ECC_BCH) { + dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n"); + break; + } default: dev_err(&pdev->dev, "Unsupported ECC mode!\n"); |