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author | Stephen Boyd | 2022-10-04 10:54:02 -0700 |
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committer | Stephen Boyd | 2022-10-04 10:54:02 -0700 |
commit | 26bebbfed5bd06fd7202fd1befa6c2c935a593e8 (patch) | |
tree | 9ae78365a75275776abcaacb4e9e6ba1344de8c6 | |
parent | a64b79c01c2836ddd8e1eb7c8173b44c3e66f999 (diff) | |
parent | 9e1343ede72af69675c103099560820e9de8fd4b (diff) | |
parent | acb84a167f14ae7d51475379ca1ff2f7bb36e2b6 (diff) | |
parent | 50cf94b419d5746b52393fa71f115e8c667a1a0f (diff) | |
parent | d772c9370fe8c3c8247dbc78dcd2f6d10eab3e18 (diff) | |
parent | 855ae87a2073ebf1b395e020de54fdf9ce7d166f (diff) |
Merge branches 'clk-rockchip', 'clk-renesas', 'clk-microchip', 'clk-allwinner' and 'clk-imx' into clk-next
* clk-rockchip:
dt-bindings: clock: rockchip: change SPDX-License-Identifier
dt-bindings: clock: convert rockchip,rk3128-cru.txt to YAML
clk: rockchip: Add clock controller support for RV1126 SoC
dt-bindings: clock: rockchip: Document RV1126 CRU
clk: rockchip: Add dt-binding header for RV1126
clk: rockchip: Add MUXTBL variant
* clk-renesas:
clk: renesas: r8a779g0: Add EtherAVB clocks
clk: renesas: r8a779g0: Add PFC/GPIO clocks
clk: renesas: r8a779g0: Add I2C clocks
clk: renesas: r8a779g0: Add watchdog clock
dt-bindings: clock: renesas,rzg2l: Document RZ/Five SoC
clk: renesas: r8a779f0: Add MSIOF clocks
clk: renesas: r9a09g011: Add IIC clock and reset entries
clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_info
clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks
clk: renesas: r8a779f0: Add CMT clocks
clk: renesas: r8a779f0: Add SDH0 clock
* clk-microchip:
clk: at91: sama5d2: Add Generic Clocks for UART/USART
clk: microchip: add PolarFire SoC fabric clock support
dt-bindings: clk: add PolarFire SoC fabric clock ids
dt-bindings: clk: document PolarFire SoC fabric clocks
dt-bindings: clk: rename mpfs-clkcfg binding
clk: microchip: mpfs: update module authorship & licencing
clk: microchip: mpfs: convert periph_clk to clk_gate
clk: microchip: mpfs: convert cfg_clk to clk_divider
clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo()
clk: microchip: mpfs: simplify control reg access
clk: microchip: mpfs: move id & offset out of clock structs
clk: microchip: mpfs: add MSS pll's set & round rate
MAINTAINERS: add polarfire soc reset controller
reset: add polarfire soc reset support
clk: microchip: mpfs: add reset controller
dt-bindings: clk: microchip: mpfs: add reset controller support
clk: microchip: mpfs: make the rtc's ahb clock critical
clk: microchip: mpfs: fix clk_cfg array bounds violation
* clk-allwinner:
clk: sunxi-ng: ccu-sun9i-a80-usb: Use dev_err_probe() helper
clk: sunxi-ng: ccu-sun9i-a80-de: Use dev_err_probe() helper
clk: sunxi-ng: sun8i-de2: Use dev_err_probe() helper
clk: sunxi-ng: d1: Limit PLL rates to stable ranges
* clk-imx:
clk: imx: scu: fix memleak on platform_device_add() fails
clk: imx93: add SAI IPG clk
clk: imx93: add MU1/2 clock
clk: imx93: switch to use new clk gate API
clk: imx: add i.MX93 clk gate
clk: imx: clk-composite-93: check white_list
clk: imx: clk-composite-93: check slice busy
dt-bindings: clock: imx93-clock: add more MU/SAI clocks
dt-bindings: clock: imx8mm: don't use multiple blank lines
clk: imx8mp: tune the order of enet_qos_root_clk