diff options
author | Ondrej Jirman | 2019-04-13 18:54:12 +0200 |
---|---|---|
committer | Linus Walleij | 2019-04-23 12:29:21 +0200 |
commit | f7275345728a0ff18a0607dd3706f2ca25dc53e0 (patch) | |
tree | 9ed152f601716f531c7efe2763e7322391f1a44f | |
parent | 483d70d73beaecab55882fcd2a357af72674e24c (diff) |
pinctrl: sunxi: Prepare for alternative bias voltage setting methods
H6 has a different I/O voltage bias setting method than A80. Prepare
existing code for using alternative bias voltage setting methods.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c | 2 | ||||
-rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c | 2 | ||||
-rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sunxi.c | 47 | ||||
-rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sunxi.h | 11 |
4 files changed, 39 insertions, 23 deletions
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c index e05dd9a5551d..a191a65217ac 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80-r.c @@ -153,7 +153,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_r_pinctrl_data = { .pin_base = PL_BASE, .irq_banks = 2, .disable_strict_mode = true, - .has_io_bias_cfg = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG, }; static int sun9i_a80_r_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c index da37d594a13d..0633a03d5e13 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c @@ -722,7 +722,7 @@ static const struct sunxi_pinctrl_desc sun9i_a80_pinctrl_data = { .npins = ARRAY_SIZE(sun9i_a80_pins), .irq_banks = 5, .disable_strict_mode = true, - .has_io_bias_cfg = true, + .io_bias_cfg_variant = BIAS_VOLTAGE_GRP_CONFIG, }; static int sun9i_a80_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index be04223591d4..98c4de5f4019 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -617,7 +617,7 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, u32 val, reg; int uV; - if (!pctl->desc->has_io_bias_cfg) + if (!pctl->desc->io_bias_cfg_variant) return 0; uV = regulator_get_voltage(supply); @@ -628,25 +628,32 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, if (uV == 0) return 0; - /* Configured value must be equal or greater to actual voltage */ - if (uV <= 1800000) - val = 0x0; /* 1.8V */ - else if (uV <= 2500000) - val = 0x6; /* 2.5V */ - else if (uV <= 2800000) - val = 0x9; /* 2.8V */ - else if (uV <= 3000000) - val = 0xA; /* 3.0V */ - else - val = 0xD; /* 3.3V */ - - pin -= pctl->desc->pin_base; - - reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); - reg &= ~IO_BIAS_MASK; - writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); - - return 0; + switch (pctl->desc->io_bias_cfg_variant) { + case BIAS_VOLTAGE_GRP_CONFIG: + /* + * Configured value must be equal or greater to actual + * voltage. + */ + if (uV <= 1800000) + val = 0x0; /* 1.8V */ + else if (uV <= 2500000) + val = 0x6; /* 2.5V */ + else if (uV <= 2800000) + val = 0x9; /* 2.8V */ + else if (uV <= 3000000) + val = 0xA; /* 3.0V */ + else + val = 0xD; /* 3.3V */ + + pin -= pctl->desc->pin_base; + + reg = readl(pctl->membase + sunxi_grp_config_reg(pin)); + reg &= ~IO_BIAS_MASK; + writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin)); + return 0; + default: + return -EINVAL; + } } static int sunxi_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index ee15ab067b5f..a62b81357136 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.h +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.h @@ -95,6 +95,15 @@ #define PINCTRL_SUN7I_A20 BIT(7) #define PINCTRL_SUN8I_R40 BIT(8) +enum sunxi_desc_bias_voltage { + BIAS_VOLTAGE_NONE, + /* + * Bias voltage configuration is done through + * Pn_GRP_CONFIG registers, as seen on A80 SoC. + */ + BIAS_VOLTAGE_GRP_CONFIG, +}; + struct sunxi_desc_function { unsigned long variant; const char *name; @@ -117,7 +126,7 @@ struct sunxi_pinctrl_desc { const unsigned int *irq_bank_map; bool irq_read_needs_mux; bool disable_strict_mode; - bool has_io_bias_cfg; + enum sunxi_desc_bias_voltage io_bias_cfg_variant; }; struct sunxi_pinctrl_function { |