diff options
| author | Jonathan Cameron | 2020-09-30 22:05:47 +0800 |
|---|---|---|
| committer | Rafael J. Wysocki | 2020-10-02 18:51:57 +0200 |
| commit | dc9e7860df91625fef04d7016182653e8f678f05 (patch) | |
| tree | abcde33ef59bafd63bfb3db9bc0f4d2d5f572907 /Documentation/admin-guide | |
| parent | b9fffe47212c70114f1d91e773ce5ecff8936ef5 (diff) | |
docs: mm: numaperf.rst Add brief description for access class 1.
Try to make minimal changes to the document which already describes
access class 0 in a generic fashion (including IO initiatiors that
are not CPUs).
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'Documentation/admin-guide')
| -rw-r--r-- | Documentation/admin-guide/mm/numaperf.rst | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/admin-guide/mm/numaperf.rst b/Documentation/admin-guide/mm/numaperf.rst index 4d69ef1de830..86f2a3c4b638 100644 --- a/Documentation/admin-guide/mm/numaperf.rst +++ b/Documentation/admin-guide/mm/numaperf.rst @@ -56,6 +56,11 @@ nodes' access characteristics share the same performance relative to other linked initiator nodes. Each target within an initiator's access class, though, do not necessarily perform the same as each other. +The access class "1" is used to allow differentiation between initiators +that are CPUs and hence suitable for generic task scheduling, and +IO initiators such as GPUs and NICs. Unlike access class 0, only +nodes containing CPUs are considered. + ================ NUMA Performance ================ @@ -88,6 +93,9 @@ The latency attributes are provided in nanoseconds. The values reported here correspond to the rated latency and bandwidth for the platform. +Access class 1 takes the same form but only includes values for CPU to +memory activity. + ========== NUMA Cache ========== |