diff options
author | Christoph Hellwig | 2022-02-23 08:47:20 +0100 |
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committer | Christoph Hellwig | 2022-02-23 08:52:50 +0100 |
commit | 1c4b5ecb7ea190fa3e9f9d6891e6c90b60e04f24 (patch) | |
tree | a9444a92909dc4929e0d1e42301e1d3dbd16c35c /Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt | |
parent | 5c1ee569660d4a205dced9cb4d0306b907fb7599 (diff) |
remove the h8300 architecture
Signed-off-by: Christoph Hellwig <hch@lst.de>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt')
-rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt | 24 |
1 files changed, 0 insertions, 24 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt b/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt deleted file mode 100644 index 399e0da22348..000000000000 --- a/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Renesas H8/300 divider clock - -Required Properties: - - - compatible: Must be "renesas,h8300-div-clock" - - - clocks: Reference to the parent clocks ("extal1" and "extal2") - - - #clock-cells: Must be 1 - - - reg: Base address and length of the divide rate selector - - - renesas,width: bit width of selector - -Example -------- - - cclk: cclk { - compatible = "renesas,h8300-div-clock"; - clocks = <&xclk>; - #clock-cells = <0>; - reg = <0xfee01b 2>; - renesas,width = <2>; - }; |