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authorJan Glauber2016-04-25 16:33:35 +0200
committerWolfram Sang2016-04-25 23:49:41 +0200
commit4729cbe038fdd321839d7780ee93ce1ccf1e7b29 (patch)
tree26b2589ca41efed5296d8f1e861a92732accbdda /Documentation/devicetree/bindings/i2c/i2c-octeon.txt
parentd1fbff8944bf88e449ae387abd498e5220a2ee10 (diff)
i2c: octeon: Add support for cn78xx chips
cn78xx has a different interrupt architecture, so we have to manage the interrupts differently. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Jan Glauber <jglauber@cavium.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'Documentation/devicetree/bindings/i2c/i2c-octeon.txt')
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-octeon.txt6
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/i2c/i2c-octeon.txt b/Documentation/devicetree/bindings/i2c/i2c-octeon.txt
index dced82ebe31d..872d485dffab 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-octeon.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-octeon.txt
@@ -4,6 +4,12 @@
Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+ or
+
+ compatible: "cavium,octeon-7890-twsi"
+
+ Compatibility with cn78XX SOCs.
+
- reg: The base address of the TWSI/I2C bus controller register bank.
- #address-cells: Must be <1>.