diff options
| author | Chao Xie | 2014-01-28 15:20:44 +0800 |
|---|---|---|
| committer | Linus Walleij | 2014-02-10 10:13:08 +0100 |
| commit | 4bd7547756af5c71d55e4d77f41db3d06c18b3e0 (patch) | |
| tree | a6806ff2060fd5f3b9d52753ab56884079f46e47 /Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt | |
| parent | b81e57e6ac35242ba59206b303ba6c7585764ee1 (diff) | |
pinctrl: single: add low power mode support
For some silicons, the pin configuration register can control
the output of the pin when the pad including the pin enter
low power mode.
For example, the pin can be "Drive 1", "Drive 0", "Float" when
the pad including the pin enter low power mode.
It is very useful when you want to control the power leakeage
when the SOC enter low power mode, and can save more power for
the low power mode.
Signed-off-by: Chao Xie <chao.xie@marvell.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt index bc0dfdfdb148..66dcaa9efd74 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt @@ -63,6 +63,13 @@ Optional properties: /* input, enable bits, disable bits, mask */ pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>; +- pinctrl-single,low-power-mode : array of value that are used to configure + low power mode of this pin. For some silicons, the low power mode will + control the output of the pin when the pad including the pin enter low + power mode. + /* low power mode value, mask */ + pinctrl-single,low-power-mode = <0x288 0x388>; + - pinctrl-single,gpio-range : list of value that are used to configure a GPIO range. They're value of subnode phandle, pin base in pinctrl device, pin number in this range, GPIO function value of this GPIO range. |