diff options
| author | Fabio Estevam | 2017-11-15 10:59:53 -0200 |
|---|---|---|
| committer | Alexandre Belloni | 2017-11-20 22:48:20 +0100 |
| commit | 87c9fd81825363237ac5560822e2261535800597 (patch) | |
| tree | 69ec6b573f7f9bbc41da2c7310c82f67d5a7b3c0 /Documentation/devicetree | |
| parent | 495bbde523969c596bcfb8285a6027c746a18ef4 (diff) | |
dt-bindings: rtc: imxdi: Improve the bindings text
Improve the bindings text by doing the following changes:
- Remove the i.MX53 reference, as the RTC on i.MX53 is a different hardware
- Add 'clocks' to the list of required properties
- Explain that the optional security violation irq is the second entry
- Use the real unit address and irq numbers for i.MX25
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Juergen Borleis <jbe@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Diffstat (limited to 'Documentation/devicetree')
| -rw-r--r-- | Documentation/devicetree/bindings/rtc/imxdi-rtc.txt | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt b/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt index 323cf26374cb..c797bc9d77d2 100644 --- a/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt +++ b/Documentation/devicetree/bindings/rtc/imxdi-rtc.txt @@ -1,20 +1,20 @@ * i.MX25 Real Time Clock controller -This binding supports the following chips: i.MX25, i.MX53 - Required properties: - compatible: should be: "fsl,imx25-rtc" - reg: physical base address of the controller and length of memory mapped region. +- clocks: should contain the phandle for the rtc clock - interrupts: rtc alarm interrupt Optional properties: -- interrupts: dryice security violation interrupt +- interrupts: dryice security violation interrupt (second entry) Example: -rtc@80056000 { - compatible = "fsl,imx53-rtc", "fsl,imx25-rtc"; - reg = <0x80056000 2000>; - interrupts = <29 56>; +rtc@53ffc000 { + compatible = "fsl,imx25-rtc"; + reg = <0x53ffc000 0x4000>; + clocks = <&clks 81>; + interrupts = <25 56>; }; |