diff options
| author | Jernej Skrabec | 2018-08-09 18:52:15 +0200 |
|---|---|---|
| committer | Maxime Ripard | 2018-08-27 09:18:09 +0200 |
| commit | b16fb66915fcfc6b1a7eb48225b6b30b69bb721b (patch) | |
| tree | ecfd56a4d164a451cfa5986d6bb2ccfaa7d5cb5b /Documentation/fpga/dfl.txt | |
| parent | 02d7901695afd1dcbec7182d878927893c07174e (diff) | |
clk: sunxi-ng: r40: Add max. rate constraint to video PLLs
Video PLLs on R40 can be set to higher rate that it is actually
supported by HW.
Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP
clock driver. Interestengly, user manual specifies maximum frequency to
be 600 MHz. Historically, this data was wrong in some user manuals for
other SoCs, so more faith is put in BSP clock driver.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'Documentation/fpga/dfl.txt')
0 files changed, 0 insertions, 0 deletions