diff options
author | Aditya Swarup | 2021-05-26 02:48:52 -0700 |
---|---|---|
committer | Matt Roper | 2021-05-27 11:05:09 -0700 |
commit | 5b26d57fdb499c2363f3d895ef008e73ec02eb9b (patch) | |
tree | 4e1482750449039ca726fb6aae37d1de325d6773 /Documentation/gpu | |
parent | 615160334f3f09d508511aae1297106fb4f49b1e (diff) |
drm/i915: Add Wa_14010733141
The WA requires the following procedure for VDBox SFC reset:
If (MFX-SFC usage is 1) {
1.Issue a MFX-SFC forced lock
2.Wait for MFX-SFC forced lock ack
3.Check the MFX-SFC usage bit
If (MFX-SFC usage bit is 1)
Reset VDBOX and SFC
else
Reset VDBOX
Release the force lock MFX-SFC
}
else if(HCP+SFC usage is 1) {
1.Issue a VE-SFC forced lock
2.Wait for SFC forced lock ack
3.Check the VE-SFC usage bit
If (VE-SFC usage bit is 1)
Reset VDBOX
else
Reset VDBOX and SFC
Release the force lock VE-SFC.
}
else
Reset VDBOX
- Restructure: the changes to the original code flow should stay
relatively minimal; we only need to do an extra HCP check after the
usual VD-MFX check and, if true, switch the register/bit we're
performing the lock on.(MattR)
v2:
- Assign unlock mask using paired_engine->mask instead of using
BIT(paired_vecs->id). (Daniele)
Bspec: 52890, 53509
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Co-developed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210526094852.286424-2-aditya.swarup@intel.com
Diffstat (limited to 'Documentation/gpu')
0 files changed, 0 insertions, 0 deletions