diff options
| author | Linus Torvalds | 2023-04-25 12:02:16 -0700 |
|---|---|---|
| committer | Linus Torvalds | 2023-04-25 12:02:16 -0700 |
| commit | a907047732470f75f3b7c9a8ee09b16765b8364c (patch) | |
| tree | c14d8b6220f80f4c87e8dc0eb6d6fa2581e9a294 /Documentation | |
| parent | 18032df5ef5c0eec2adf120142bd95a3a8807866 (diff) | |
| parent | 4c87f3ff78b20da0dd118762fd66b67a98e36249 (diff) | |
Merge tag 'soc-drivers-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC driver updates from Arnd Bergmann:
"The most notable updates this time are for Qualcomm Snapdragon
platforms. The Inline-Crypto-Engine gets a new DT binding and driver,
and a number of drivers now support additional Snapdragon variants, in
particular the rsc, scm, geni, bwm, glink and socinfo, while the llcc
(edac) and rpm drivers get notable functionality updates.
Updates on other platforms include:
- Various updates to the Mediatek mutex and mmsys drivers, including
support for the Helio X10 SoC
- Support for unidirectional mailbox channels in Arm SCMI firmware
- Support for per cpu asynchronous notification in OP-TEE firmware
- Minor updates for memory controller drivers.
- Minor updates for Renesas, TI, Amlogic, Apple, Broadcom, Tegra,
Allwinner, Versatile Express, Canaan, Microchip, Mediatek and i.MX
SoC drivers, mainly updating the use of MODULE_LICENSE() macros and
obsolete DT driver interfaces"
* tag 'soc-drivers-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (165 commits)
soc: ti: smartreflex: Simplify getting the opam_sr pointer
bus: vexpress-config: Add explicit of_platform.h include
soc: mediatek: Kconfig: Add MTK_CMDQ dependency to MTK_MMSYS
memory: mtk-smi: mt8365: Add SMI Support
dt-bindings: memory-controllers: mediatek,smi-larb: add mt8365
dt-bindings: memory-controllers: mediatek,smi-common: add mt8365
memory: tegra: read values from correct device
dt-bindings: crypto: Add Qualcomm Inline Crypto Engine
soc: qcom: Make the Qualcomm UFS/SDCC ICE a dedicated driver
dt-bindings: firmware: document Qualcomm QCM2290 SCM
soc: qcom: rpmh-rsc: Support RSC v3 minor versions
soc: qcom: smd-rpm: Use GFP_ATOMIC in write path
soc/tegra: fuse: Remove nvmem root only access
soc/tegra: cbb: tegra194: Use of_address_count() helper
soc/tegra: cbb: Remove MODULE_LICENSE in non-modules
ARM: tegra: Remove MODULE_LICENSE in non-modules
soc/tegra: flowctrl: Use devm_platform_get_and_ioremap_resource()
soc: tegra: cbb: Drop empty platform remove function
firmware: arm_scmi: Add support for unidirectional mailbox channels
dt-bindings: firmware: arm,scmi: Support mailboxes unidirectional channels
...
Diffstat (limited to 'Documentation')
22 files changed, 352 insertions, 59 deletions
diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml index 1748f1605cc7..7dff32f373cb 100644 --- a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml @@ -2,8 +2,8 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Meson Firmware registers Interface diff --git a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml index eee7cda9f91b..09b27e98d4c9 100644 --- a/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-mx-secbus2.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/arm/amlogic/amlogic,meson-mx-secbus2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Meson8/Meson8b/Meson8m2 SECBUS2 register interface diff --git a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml index d4dc0749f9fd..5d033570b57b 100644 --- a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml +++ b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml @@ -28,7 +28,8 @@ properties: maxItems: 1 description: | This interrupt which is used to signal an event by the secure world - software is expected to be edge-triggered. + software is expected to be either a per-cpu interrupt or an + edge-triggered peripheral interrupt. method: enum: [smc, hvc] diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..02cc6894eb13 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Last Level Cache Controller maintainers: - - Rishabh Bhatnagar <rishabhb@codeaurora.org> - - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> + - Bjorn Andersson <andersson@kernel.org> description: | LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, @@ -27,6 +26,7 @@ properties: - qcom,sc8280xp-llcc - qcom,sdm845-llcc - qcom,sm6350-llcc + - qcom,sm7150-llcc - qcom,sm8150-llcc - qcom,sm8250-llcc - qcom,sm8350-llcc @@ -34,14 +34,12 @@ properties: - qcom,sm8550-llcc reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region + minItems: 2 + maxItems: 9 reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base + minItems: 2 + maxItems: 9 interrupts: maxItems: 1 @@ -51,15 +49,120 @@ required: - reg - reg-names +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-llcc + - qcom,sm6350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC6 base register region + - description: LLCC7 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc4_base + - const: llcc5_base + - const: llcc6_base + - const: llcc7_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc_broadcast_base + additionalProperties: false examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> - system-cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; + interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; + }; }; diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml new file mode 100644 index 000000000000..92e1d76e29ee --- /dev/null +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/crypto/qcom,inline-crypto-engine.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine + +maintainers: + - Bjorn Andersson <andersson@kernel.org> + +properties: + compatible: + items: + - enum: + - qcom,sm8550-inline-crypto-engine + - const: qcom,inline-crypto-engine + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sm8550-gcc.h> + + crypto@1d88000 { + compatible = "qcom,sm8550-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0x01d88000 0x8000>; + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; +... diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml index 2f7c51c75e85..5824c43e9893 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -56,17 +56,38 @@ properties: description: Specifies the mailboxes used to communicate with SCMI compliant firmware. - items: - - const: tx - - const: rx + oneOf: + - items: + - const: tx + - const: rx + minItems: 1 + - items: + - const: tx + - const: tx_reply + - const: rx + minItems: 2 mboxes: description: List of phandle and mailbox channel specifiers. It should contain - exactly one or two mailboxes, one for transmitting messages("tx") - and another optional for receiving the notifications("rx") if supported. + exactly one, two or three mailboxes; the first one or two for transmitting + messages ("tx") and another optional ("rx") for receiving notifications + and delayed responses, if supported by the platform. + The number of mailboxes needed for transmitting messages depends on the + type of channels exposed by the specific underlying mailbox controller; + one single channel descriptor is enough if such channel is bidirectional, + while two channel descriptors are needed to represent the SCMI ("tx") + channel if the underlying mailbox channels are of unidirectional type. + The effective combination in numbers of mboxes and shmem descriptors let + the SCMI subsystem determine unambiguosly which type of SCMI channels are + made available by the underlying mailbox controller and how to use them. + 1 mbox / 1 shmem => SCMI TX over 1 mailbox bidirectional channel + 2 mbox / 2 shmem => SCMI TX and RX over 2 mailbox bidirectional channels + 2 mbox / 1 shmem => SCMI TX over 2 mailbox unidirectional channels + 3 mbox / 2 shmem => SCMI TX and RX over 3 mailbox unidirectional channels + Any other combination of mboxes and shmem is invalid. minItems: 1 - maxItems: 2 + maxItems: 3 shmem: description: @@ -228,13 +249,20 @@ $defs: maxItems: 1 mbox-names: - items: - - const: tx - - const: rx + oneOf: + - items: + - const: tx + - const: rx + minItems: 1 + - items: + - const: tx + - const: tx_reply + - const: rx + minItems: 2 mboxes: minItems: 1 - maxItems: 2 + maxItems: 3 shmem: minItems: 1 diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index a66e99812b1f..367d04ad1923 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -24,9 +24,11 @@ properties: - qcom,scm-apq8064 - qcom,scm-apq8084 - qcom,scm-ipq4019 + - qcom,scm-ipq5332 - qcom,scm-ipq6018 - qcom,scm-ipq806x - qcom,scm-ipq8074 + - qcom,scm-ipq9574 - qcom,scm-mdm9607 - qcom,scm-msm8226 - qcom,scm-msm8660 @@ -38,10 +40,12 @@ properties: - qcom,scm-msm8994 - qcom,scm-msm8996 - qcom,scm-msm8998 + - qcom,scm-qcm2290 - qcom,scm-qdu1000 - qcom,scm-sa8775p - qcom,scm-sc7180 - qcom,scm-sc7280 + - qcom,scm-sc8180x - qcom,scm-sc8280xp - qcom,scm-sdm670 - qcom,scm-sdm845 @@ -107,6 +111,7 @@ allOf: - qcom,scm-msm8960 - qcom,scm-msm8974 - qcom,scm-msm8976 + - qcom,scm-qcm2290 - qcom,scm-sm6375 then: required: @@ -125,6 +130,7 @@ allOf: - qcom,scm-apq8064 - qcom,scm-msm8660 - qcom,scm-msm8960 + - qcom,scm-qcm2290 - qcom,scm-sm6375 then: properties: @@ -166,6 +172,7 @@ allOf: compatible: contains: enum: + - qcom,scm-qdu1000 - qcom,scm-sm8450 - qcom,scm-sm8550 then: diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml index a8fda30cccbb..2f36ac23604c 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml @@ -43,6 +43,7 @@ properties: - mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vpp - mediatek,mt8195-smi-sub-common + - mediatek,mt8365-smi-common - description: for mt7623 items: @@ -133,6 +134,7 @@ allOf: - mediatek,mt8192-smi-common - mediatek,mt8195-smi-common-vdo - mediatek,mt8195-smi-common-vpp + - mediatek,mt8365-smi-common then: properties: diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml index 5f4ac3609887..aee7f6cf1300 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml @@ -34,6 +34,10 @@ properties: - const: mediatek,mt7623-smi-larb - const: mediatek,mt2701-smi-larb + - items: + - const: mediatek,mt8365-smi-larb + - const: mediatek,mt8186-smi-larb + reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml index 7056ccb7eb30..8e3822314b25 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/memory-controllers/renesas,dbsc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Renesas DDR Bus Controllers diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml index 30a403b1b79a..56e62cd0b36a 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml @@ -20,7 +20,7 @@ description: | - if it contains "cfi-flash", then HyperFlash is used. allOf: - - $ref: "/schemas/spi/spi-controller.yaml#" + - $ref: /schemas/spi/spi-controller.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml index 098348b2b815..783ac984d898 100644 --- a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml @@ -42,7 +42,7 @@ properties: maxItems: 8 devfreq-events: - $ref: '/schemas/types.yaml#/definitions/phandle-array' + $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 maxItems: 16 items: @@ -50,7 +50,7 @@ properties: description: phandles of the PPMU events used by the controller. device-handle: - $ref: '/schemas/types.yaml#/definitions/phandle' + $ref: /schemas/types.yaml#/definitions/phandle description: | phandle of the connected DRAM memory device. For more information please refer to jedec,lpddr3.yaml. @@ -73,7 +73,7 @@ properties: - description: registers of DREX1 samsung,syscon-clk: - $ref: '/schemas/types.yaml#/definitions/phandle' + $ref: /schemas/types.yaml#/definitions/phandle description: | Phandle of the clock register set used by the controller, these registers are used for enabling a 'pause' feature and are not exposed by clock diff --git a/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml b/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml index c3c599096353..cd06865e1f2a 100644 --- a/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml +++ b/Documentation/devicetree/bindings/soc/amlogic/amlogic,canvas.yaml @@ -2,8 +2,8 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/soc/amlogic/amlogic,canvas.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/soc/amlogic/amlogic,canvas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Canvas Video Lookup Table diff --git a/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml new file mode 100644 index 000000000000..77c281153010 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/amlogic/amlogic,meson-gx-clk-measure.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/amlogic/amlogic,meson-gx-clk-measure.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic Internal Clock Measurer + +description: + The Amlogic SoCs contains an IP to measure the internal clocks. + The precision is multiple of MHz, useful to debug the clock states. + +maintainers: + - Neil Armstrong <neil.armstrong@linaro.org> + +properties: + compatible: + enum: + - amlogic,meson-gx-clk-measure + - amlogic,meson8-clk-measure + - amlogic,meson8b-clk-measure + - amlogic,meson-axg-clk-measure + - amlogic,meson-g12a-clk-measure + - amlogic,meson-sm1-clk-measure + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + clock-measure@8758 { + compatible = "amlogic,meson-gx-clk-measure"; + reg = <0x8758 0x10>; + }; diff --git a/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt b/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt deleted file mode 100644 index 3dd563cec794..000000000000 --- a/Documentation/devicetree/bindings/soc/amlogic/clk-measure.txt +++ /dev/null @@ -1,21 +0,0 @@ -Amlogic Internal Clock Measurer -=============================== - -The Amlogic SoCs contains an IP to measure the internal clocks. -The precision is multiple of MHz, useful to debug the clock states. - -Required properties: -- compatible: Shall contain one of the following : - "amlogic,meson-gx-clk-measure" for GX SoCs - "amlogic,meson8-clk-measure" for Meson8 SoCs - "amlogic,meson8b-clk-measure" for Meson8b SoCs - "amlogic,meson-axg-clk-measure" for AXG SoCs - "amlogic,meson-g12a-clk-measure" for G12a SoCs - "amlogic,meson-sm1-clk-measure" for SM1 SoCs -- reg: base address and size of the Clock Measurer register space. - -Example: - clock-measure@8758 { - compatible = "amlogic,meson-gx-clk-measure"; - reg = <0x0 0x8758 0x0 0x10>; - }; diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index 15c133cac315..ba2014a8725c 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -35,6 +35,8 @@ properties: - mediatek,mt8188-disp-mutex - mediatek,mt8192-disp-mutex - mediatek,mt8195-disp-mutex + - mediatek,mt8195-vpp-mutex + - mediatek,mt8365-disp-mutex reg: maxItems: 1 @@ -70,12 +72,30 @@ properties: 4 arguments defined in this property. Each GCE subsys id is mapping to a client defined in the header include/dt-bindings/gce/<chip>-gce.h. +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt2701-disp-mutex + - mediatek,mt2712-disp-mutex + - mediatek,mt6795-disp-mutex + - mediatek,mt8173-disp-mutex + - mediatek,mt8186-disp-mutex + - mediatek,mt8186-mdp3-mutex + - mediatek,mt8192-disp-mutex + - mediatek,mt8195-disp-mutex + then: + required: + - clocks + + required: - compatible - reg - interrupts - power-domains - - clocks additionalProperties: false diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml index ab607efbb64c..798f15588ee2 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml @@ -25,6 +25,7 @@ properties: compatible: items: - enum: + - qcom,qdu1000-aoss-qmp - qcom,sc7180-aoss-qmp - qcom,sc7280-aoss-qmp - qcom,sc8180x-aoss-qmp diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml index 6026c21736d8..4502458b0669 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,apr.yaml @@ -62,7 +62,14 @@ properties: maxItems: 1 qcom,intents: - $ref: /schemas/types.yaml#/definitions/uint32-array + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 32 + items: + items: + - description: size of each intent to preallocate + - description: amount of intents to preallocate + minimum: 1 description: List of (size, amount) pairs describing what intents should be preallocated for this virtual channel. This can be used to tweak the diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index cf863683c21a..6440dc801387 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -25,6 +25,8 @@ properties: - qcom,sc8180x-pmic-glink - qcom,sc8280xp-pmic-glink - qcom,sm8350-pmic-glink + - qcom,sm8450-pmic-glink + - qcom,sm8550-pmic-glink - const: qcom,pmic-glink '#address-cells': diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index 16fd67c0bd1f..94765fbc868e 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -33,6 +33,7 @@ properties: enum: - qcom,rpm-apq8084 - qcom,rpm-ipq6018 + - qcom,rpm-ipq9574 - qcom,rpm-msm8226 - qcom,rpm-msm8909 - qcom,rpm-msm8916 @@ -40,6 +41,7 @@ properties: - qcom,rpm-msm8953 - qcom,rpm-msm8974 - qcom,rpm-msm8976 + - qcom,rpm-msm8994 - qcom,rpm-msm8996 - qcom,rpm-msm8998 - qcom,rpm-sdm660 @@ -84,6 +86,7 @@ if: - qcom,rpm-msm8974 - qcom,rpm-msm8976 - qcom,rpm-msm8953 + - qcom,rpm-msm8994 then: properties: qcom,glink-channels: false diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml index ba694ce4a037..0548e8e0d30b 100644 --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml @@ -26,6 +26,7 @@ properties: - qcom,sdm845-imem - qcom,sdx55-imem - qcom,sdx65-imem + - qcom,sm6375-imem - qcom,sm8450-imem - const: syscon - const: simple-mfd diff --git a/Documentation/staging/tee.rst b/Documentation/staging/tee.rst index 498343c7ab08..22baa077a3b9 100644 --- a/Documentation/staging/tee.rst +++ b/Documentation/staging/tee.rst @@ -214,6 +214,57 @@ call is done from the thread assisting the interrupt handler. This is a building block for OP-TEE OS in secure world to implement the top half and bottom half style of device drivers. +OPTEE_INSECURE_LOAD_IMAGE Kconfig option +---------------------------------------- + +The OPTEE_INSECURE_LOAD_IMAGE Kconfig option enables the ability to load the +BL32 OP-TEE image from the kernel after the kernel boots, rather than loading +it from the firmware before the kernel boots. This also requires enabling the +corresponding option in Trusted Firmware for Arm. The Trusted Firmware for Arm +documentation [8] explains the security threat associated with enabling this as +well as mitigations at the firmware and platform level. + +There are additional attack vectors/mitigations for the kernel that should be +addressed when using this option. + +1. Boot chain security. + + * Attack vector: Replace the OP-TEE OS image in the rootfs to gain control of + the system. + + * Mitigation: There must be boot chain security that verifies the kernel and + rootfs, otherwise an attacker can modify the loaded OP-TEE binary by + modifying it in the rootfs. + +2. Alternate boot modes. + + * Attack vector: Using an alternate boot mode (i.e. recovery mode), the + OP-TEE driver isn't loaded, leaving the SMC hole open. + + * Mitigation: If there are alternate methods of booting the device, such as a + recovery mode, it should be ensured that the same mitigations are applied + in that mode. + +3. Attacks prior to SMC invocation. + + * Attack vector: Code that is executed prior to issuing the SMC call to load + OP-TEE can be exploited to then load an alternate OS image. + + * Mitigation: The OP-TEE driver must be loaded before any potential attack + vectors are opened up. This should include mounting of any modifiable + filesystems, opening of network ports or communicating with external + devices (e.g. USB). + +4. Blocking SMC call to load OP-TEE. + + * Attack vector: Prevent the driver from being probed, so the SMC call to + load OP-TEE isn't executed when desired, leaving it open to being executed + later and loading a modified OS. + + * Mitigation: It is recommended to build the OP-TEE driver as builtin driver + rather than as a module to prevent exploits that may cause the module to + not be loaded. + AMD-TEE driver ============== @@ -309,3 +360,5 @@ References [6] include/linux/psp-tee.h [7] drivers/tee/amdtee/amdtee_if.h + +[8] https://trustedfirmware-a.readthedocs.io/en/latest/threat_model/threat_model.html |