diff options
| author | Linus Torvalds | 2020-10-15 09:51:18 -0700 |
|---|---|---|
| committer | Linus Torvalds | 2020-10-15 09:51:18 -0700 |
| commit | c6dbef7307629cce855aa6b482b60cbf7777ed88 (patch) | |
| tree | d8d13630bd57090173ad9f0c5f8e3bfb392964c9 /Documentation | |
| parent | ade7afe3e606f9f6ff0e6deefce140157f75540b (diff) | |
| parent | 93578a25d4e21603518daf27a5f9caa4bf79de68 (diff) | |
Merge tag 'usb-5.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb
Pull USB/PHY/Thunderbolt driver updates from Greg KH:
"Here is the big set of USB, PHY, and Thunderbolt driver updates for
5.10-rc1.
Lots of tiny different things for these subsystems are in here,
including:
- phy driver updates
- thunderbolt / USB 4 updates and additions
- USB gadget driver updates
- xhci fixes and updates
- typec driver additions and updates
- api conversions to various drivers for core kernel api changes
- new USB control message functions to make it harder to get wrong,
as found by syzbot (took 2 tries to get it right)
- lots of tiny USB driver fixes and updates all over the place
All of these have been in linux-next for a while, with the exception
of the last "obviously correct" patch that updated a FALLTHROUGH
comment that got merged last weekend"
* tag 'usb-5.10-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (374 commits)
usb: musb: gadget: Use fallthrough pseudo-keyword
usb: typec: Add QCOM PMIC typec detection driver
USB: serial: option: add Cellient MPL200 card
usb: typec: tcpci_maxim: Add support for Sink FRS
usb: typec: tcpci: Implement callbacks for FRS
usb: typec: tcpm: Add support for Sink Fast Role SWAP(FRS)
usb: typec: tcpci_maxim: Chip level TCPC driver
usb: typec: tcpci: Add set_vbus tcpci callback
usb: typec: tcpci: Add a getter method to retrieve tcpm_port reference
usbip: vhci_hcd: fix calling usb_hcd_giveback_urb() with irqs enabled
usb: cdc-acm: add quirk to blacklist ETAS ES58X devices
USB: serial: ftdi_sio: use cur_altsetting for consistency
USB: serial: option: Add Telit FT980-KS composition
USB: core: remove polling for /sys/kernel/debug/usb/devices
usb: typec: add support for STUSB160x Type-C controller family
usb: typec: add typec_find_pwr_opmode
usb: typec: hd3ss3220: Use OF graph API to get the connector fwnode
dt-bindings: usb: renesas,usb3-peri: Document HS and SS data bus
dt-bindings: usb: convert ti,hd3ss3220 bindings to json-schema
usb: dwc2: Fix INTR OUT transfers in DDMA mode.
...
Diffstat (limited to 'Documentation')
24 files changed, 840 insertions, 159 deletions
diff --git a/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml b/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml index 9fdb319dcf19..a2c63c8b1d10 100644 --- a/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml @@ -48,6 +48,22 @@ properties: - compatible - "#clock-cells" + reset: + type: object + + properties: + compatible: + const: raspberrypi,firmware-reset + + "#reset-cells": + const: 1 + description: > + The argument is the ID of the firmware reset line to affect. + + required: + - compatible + - "#reset-cells" + additionalProperties: false required: @@ -66,5 +82,10 @@ examples: compatible = "raspberrypi,firmware-clocks"; #clock-cells = <1>; }; + + reset: reset { + compatible = "raspberrypi,firmware-reset"; + #reset-cells = <1>; + }; }; ... diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt index ed47e5cd067e..7c70f2ad9942 100644 --- a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt @@ -1,7 +1,7 @@ * Freescale i.MX8MQ USB3 PHY binding Required properties: -- compatible: Should be "fsl,imx8mq-usb-phy" +- compatible: Should be "fsl,imx8mq-usb-phy" or "fsl,imx8mp-usb-phy" - #phys-cells: must be 0 (see phy-bindings.txt in this directory) - reg: The base address and length of the registers - clocks: phandles to the clocks for each clock listed in clock-names diff --git a/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml index 77bb5309918e..edd9d70a672a 100644 --- a/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml +++ b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml @@ -23,7 +23,9 @@ description: |+ properties: compatible: - const: intel,lgm-emmc-phy + oneOf: + - const: intel,lgm-emmc-phy + - const: intel,keembay-emmc-phy "#phy-cells": const: 0 @@ -34,6 +36,10 @@ properties: clocks: maxItems: 1 + clock-names: + items: + - const: emmcclk + required: - "#phy-cells" - compatible @@ -57,4 +63,13 @@ examples: #phy-cells = <0>; }; }; + + - | + phy@20290000 { + compatible = "intel,keembay-emmc-phy"; + reg = <0x20290000 0x54>; + clocks = <&emmc>; + clock-names = "emmcclk"; + #phy-cells = <0>; + }; ... diff --git a/Documentation/devicetree/bindings/phy/intel,lgm-usb-phy.yaml b/Documentation/devicetree/bindings/phy/intel,lgm-usb-phy.yaml new file mode 100644 index 000000000000..ce62c0b94daf --- /dev/null +++ b/Documentation/devicetree/bindings/phy/intel,lgm-usb-phy.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/intel,lgm-usb-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel LGM USB PHY Device Tree Bindings + +maintainers: + - Vadivel Murugan Ramuthevar <vadivel.muruganx.ramuthevar@linux.intel.com> + +properties: + compatible: + const: intel,lgm-usb-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + items: + - description: USB PHY and Host controller reset + - description: APB BUS reset + - description: General Hardware reset + + reset-names: + items: + - const: phy + - const: apb + - const: phy31 + + "#phy-cells": + const: 0 + +required: + - compatible + - clocks + - reg + - resets + - reset-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + usb-phy@e7e00000 { + compatible = "intel,lgm-usb-phy"; + reg = <0xe7e00000 0x10000>; + clocks = <&cgu0 153>; + resets = <&rcu 0x70 0x24>, + <&rcu 0x70 0x26>, + <&rcu 0x70 0x28>; + reset-names = "phy", "apb", "phy31"; + #phy-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml index 4071438be2ba..e266ade53d87 100644 --- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml +++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml @@ -4,11 +4,13 @@ $id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Cadence Torrent SD0801 PHY binding for DisplayPort +title: Cadence Torrent SD0801 PHY binding description: This binding describes the Cadence SD0801 PHY (also known as Torrent PHY) - hardware included with the Cadence MHDP DisplayPort controller. + hardware included with the Cadence MHDP DisplayPort controller. Torrent + PHY also supports multilink multiprotocol combinations including protocols + such as PCIe, USB, SGMII, QSGMII etc. maintainers: - Swapnil Jakhade <sjakhade@cadence.com> @@ -49,13 +51,21 @@ properties: - const: dptx_phy resets: - maxItems: 1 - description: - Torrent PHY reset. - See Documentation/devicetree/bindings/reset/reset.txt + minItems: 1 + maxItems: 2 + items: + - description: Torrent PHY reset. + - description: Torrent APB reset. This is optional. + + reset-names: + minItems: 1 + maxItems: 2 + items: + - const: torrent_reset + - const: torrent_apb patternProperties: - '^phy@[0-7]+$': + '^phy@[0-3]$': type: object description: Each group of PHY lanes with a single master lane should be represented as a sub-node. @@ -63,6 +73,8 @@ patternProperties: reg: description: The master lane number. This is the lowest numbered lane in the lane group. + minimum: 0 + maximum: 3 resets: minItems: 1 @@ -78,15 +90,25 @@ patternProperties: Specifies the type of PHY for which the group of PHY lanes is used. Refer include/dt-bindings/phy/phy.h. Constants from the header should be used. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 2, 3, 4, 5, 6] + minimum: 1 + maximum: 9 cdns,num-lanes: description: - Number of DisplayPort lanes. + Number of lanes. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 2, 4] + enum: [1, 2, 3, 4] default: 4 + cdns,ssc-mode: + description: + Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC, + EXTERNAL_SSC or INTERNAL_SSC. + Refer include/dt-bindings/phy/phy-cadence-torrent.h for the constants to be used. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + default: 0 + cdns,max-bit-rate: description: Maximum DisplayPort link bit rate to use, in Mbps @@ -99,6 +121,7 @@ patternProperties: - resets - "#phy-cells" - cdns,phy-type + - cdns,num-lanes additionalProperties: false @@ -111,6 +134,7 @@ required: - reg - reg-names - resets + - reset-names additionalProperties: false @@ -128,18 +152,56 @@ examples: <0xf0 0xfb030a00 0x0 0x00000040>; reg-names = "torrent_phy", "dptx_phy"; resets = <&phyrst 0>; + reset-names = "torrent_reset"; clocks = <&ref_clk>; clock-names = "refclk"; #address-cells = <1>; #size-cells = <0>; phy@0 { - reg = <0>; - resets = <&phyrst 1>, <&phyrst 2>, - <&phyrst 3>, <&phyrst 4>; - #phy-cells = <0>; - cdns,phy-type = <PHY_TYPE_DP>; - cdns,num-lanes = <4>; - cdns,max-bit-rate = <8100>; + reg = <0>; + resets = <&phyrst 1>, <&phyrst 2>, + <&phyrst 3>, <&phyrst 4>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_DP>; + cdns,num-lanes = <4>; + cdns,max-bit-rate = <8100>; + }; + }; + }; + - | + #include <dt-bindings/phy/phy.h> + #include <dt-bindings/phy/phy-cadence-torrent.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + torrent-phy@f0fb500000 { + compatible = "cdns,torrent-phy"; + reg = <0xf0 0xfb500000 0x0 0x00100000>; + reg-names = "torrent_phy"; + resets = <&phyrst 0>, <&phyrst 1>; + reset-names = "torrent_reset", "torrent_apb"; + clocks = <&ref_clk>; + clock-names = "refclk"; + #address-cells = <1>; + #size-cells = <0>; + phy@0 { + reg = <0>; + resets = <&phyrst 2>, <&phyrst 3>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + cdns,num-lanes = <2>; + cdns,ssc-mode = <TORRENT_SERDES_NO_SSC>; + }; + + phy@2 { + reg = <2>; + resets = <&phyrst 4>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_SGMII>; + cdns,num-lanes = <1>; + cdns,ssc-mode = <TORRENT_SERDES_NO_SSC>; }; }; }; diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml index ef8ae9f73092..33974ad10afe 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml @@ -13,17 +13,21 @@ maintainers: properties: compatible: enum: + - qcom,sc7180-qmp-usb3-dp-phy - qcom,sc7180-qmp-usb3-phy + - qcom,sdm845-qmp-usb3-dp-phy - qcom,sdm845-qmp-usb3-phy reg: items: - - description: Address and length of PHY's common serdes block. + - description: Address and length of PHY's USB serdes block. - description: Address and length of the DP_COM control block. + - description: Address and length of PHY's DP serdes block. reg-names: items: - - const: reg-base + - const: usb - const: dp_com + - const: dp "#clock-cells": enum: [ 1, 2 ] @@ -74,16 +78,74 @@ properties: #Required nodes: patternProperties: - "^phy@[0-9a-f]+$": + "^usb3-phy@[0-9a-f]+$": type: object description: - Each device node of QMP phy is required to have as many child nodes as - the number of lanes the PHY has. + The USB3 PHY. + + properties: + reg: + items: + - description: Address and length of TX. + - description: Address and length of RX. + - description: Address and length of PCS. + - description: Address and length of TX2. + - description: Address and length of RX2. + - description: Address and length of pcs_misc. + + clocks: + items: + - description: pipe clock + + clock-names: + items: + - const: pipe0 + + clock-output-names: + items: + - const: usb3_phy_pipe_clk_src + + '#clock-cells': + const: 0 + + '#phy-cells': + const: 0 + + required: + - reg + - clocks + - clock-names + - '#clock-cells' + - '#phy-cells' + + "^dp-phy@[0-9a-f]+$": + type: object + description: + The DP PHY. + + properties: + reg: + items: + - description: Address and length of TX. + - description: Address and length of RX. + - description: Address and length of PCS. + - description: Address and length of TX2. + - description: Address and length of RX2. + + '#clock-cells': + const: 1 + + '#phy-cells': + const: 0 + + required: + - reg + - '#clock-cells' + - '#phy-cells' required: - compatible - reg - - reg-names - "#clock-cells" - "#address-cells" - "#size-cells" @@ -101,14 +163,15 @@ examples: - | #include <dt-bindings/clock/qcom,gcc-sdm845.h> usb_1_qmpphy: phy-wrapper@88e9000 { - compatible = "qcom,sdm845-qmp-usb3-phy"; + compatible = "qcom,sdm845-qmp-usb3-dp-phy"; reg = <0x088e9000 0x18c>, - <0x088e8000 0x10>; - reg-names = "reg-base", "dp_com"; + <0x088e8000 0x10>, + <0x088ea000 0x40>; + reg-names = "usb", "dp_com", "dp"; #clock-cells = <1>; #address-cells = <1>; #size-cells = <1>; - ranges = <0x0 0x088e9000 0x1000>; + ranges = <0x0 0x088e9000 0x2000>; clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, @@ -123,7 +186,7 @@ examples: vdda-phy-supply = <&vdda_usb2_ss_1p2>; vdda-pll-supply = <&vdda_usb2_ss_core>; - phy@200 { + usb3-phy@200 { reg = <0x200 0x128>, <0x400 0x200>, <0xc00 0x218>, @@ -136,4 +199,14 @@ examples: clock-names = "pipe0"; clock-output-names = "usb3_phy_pipe_clk_src"; }; + + dp-phy@88ea200 { + reg = <0xa200 0x200>, + <0xa400 0x200>, + <0xaa00 0x200>, + <0xa600 0x200>, + <0xa800 0x200>; + #clock-cells = <1>; + #phy-cells = <0>; + }; }; diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml new file mode 100644 index 000000000000..bab2ff4d9dc9 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/socionext,uniphier-ahci-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Socionext UniPhier AHCI PHY + +description: | + This describes the deivcetree bindings for PHY interfaces built into + AHCI controller implemented on Socionext UniPhier SoCs. + +maintainers: + - Kunihiko Hayashi <hayashi.kunihiko@socionext.com> + +properties: + compatible: + enum: + - socionext,uniphier-pxs2-ahci-phy + - socionext,uniphier-pxs3-ahci-phy + + reg: + description: PHY register region (offset and length) + + "#phy-cells": + const: 0 + + clocks: + maxItems: 2 + + clock-names: + oneOf: + - items: # for PXs2 + - const: link + - items: # for others + - const: link + - const: phy + + resets: + maxItems: 2 + + reset-names: + items: + - const: link + - const: phy + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + ahci-glue@65700000 { + compatible = "socionext,uniphier-pxs3-ahci-glue", + "simple-mfd"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x65700000 0x100>; + + ahci_phy: phy@10 { + compatible = "socionext,uniphier-pxs3-ahci-phy"; + reg = <0x10 0x10>; + #phy-cells = <0>; + clock-names = "link", "phy"; + clocks = <&sys_clk 28>, <&sys_clk 30>; + reset-names = "link", "phy"; + resets = <&sys_rst 28>, <&sys_rst 30>; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml b/Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml new file mode 100644 index 000000000000..15207ca9548f --- /dev/null +++ b/Documentation/devicetree/bindings/phy/ti,omap-usb2.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/ti,omap-usb2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OMAP USB2 PHY + +maintainers: + - Kishon Vijay Abraham I <kishon@ti.com> + - Roger Quadros <rogerq@ti.com> + +properties: + compatible: + oneOf: + - items: + - enum: + - ti,dra7x-usb2 + - ti,dra7x-usb2-phy2 + - ti,am654-usb2 + - enum: + - ti,omap-usb2 + - items: + - const: ti,am437x-usb2 + - items: + - const: ti,omap-usb2 + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + clocks: + minItems: 1 + items: + - description: wakeup clock + - description: reference clock + + clock-names: + minItems: 1 + items: + - const: wkupclk + - const: refclk + + syscon-phy-power: + $ref: /schemas/types.yaml#definitions/phandle-array + description: + phandle/offset pair. Phandle to the system control module and + register offset to power on/off the PHY. + + ctrl-module: + $ref: /schemas/types.yaml#definitions/phandle + description: + (deprecated) phandle of the control module used by PHY driver + to power on the PHY. Use syscon-phy-power instead. + +required: + - compatible + - reg + - "#phy-cells" + - clocks + - clock-names + +examples: + - | + usb0_phy: phy@4100000 { + compatible = "ti,am654-usb2", "ti,omap-usb2"; + reg = <0x4100000 0x54>; + syscon-phy-power = <&scm_conf 0x4000>; + clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; + clock-names = "wkupclk", "refclk"; + #phy-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index 5ffc95c62909..c33e9bc79521 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -45,9 +45,15 @@ properties: ranges: true assigned-clocks: + minItems: 1 maxItems: 2 assigned-clock-parents: + minItems: 1 + maxItems: 2 + + assigned-clock-rates: + minItems: 1 maxItems: 2 typec-dir-gpios: @@ -119,9 +125,10 @@ patternProperties: logic. properties: clocks: + minItems: 2 maxItems: 4 - description: Phandle to four clock nodes representing the inputs to - refclk_dig + description: Phandle to two (Torrent) or four (Sierra) clock nodes representing + the inputs to refclk_dig "#clock-cells": const: 0 @@ -203,7 +210,7 @@ examples: }; refclk-dig { - clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, + clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>; #clock-cells = <0>; assigned-clocks = <&wiz0_refclk_dig>; diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt index 8f93c3b694a7..60c9d0ac75e6 100644 --- a/Documentation/devicetree/bindings/phy/ti-phy.txt +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt @@ -27,43 +27,6 @@ omap_control_usb: omap-control-usb@4a002300 { reg-names = "otghs_control"; }; -OMAP USB2 PHY - -Required properties: - - compatible: Should be "ti,omap-usb2" - Should be "ti,dra7x-usb2" for the 1st instance of USB2 PHY on - DRA7x - Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY - in DRA7x - Should be "ti,am654-usb2" for the USB2 PHYs on AM654. - - reg : Address and length of the register set for the device. - - #phy-cells: determine the number of cells that should be given in the - phandle while referencing this phy. - - clocks: a list of phandles and clock-specifier pairs, one for each entry in - clock-names. - - clock-names: should include: - * "wkupclk" - wakeup clock. - * "refclk" - reference clock (optional). - -Deprecated properties: - - ctrl-module : phandle of the control module used by PHY driver to power on - the PHY. - -Recommended properies: -- syscon-phy-power : phandle/offset pair. Phandle to the system control - module and the register offset to power on/off the PHY. - -This is usually a subnode of ocp2scp to which it is connected. - -usb2phy@4a0ad080 { - compatible = "ti,omap-usb2"; - reg = <0x4a0ad080 0x58>; - ctrl-module = <&omap_control_usb>; - #phy-cells = <0>; - clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>; - clock-names = "wkupclk", "refclk"; -}; - TI PIPE3 PHY Required properties: diff --git a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml index 5b04a7dfa018..c0058332b967 100644 --- a/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml +++ b/Documentation/devicetree/bindings/usb/amlogic,meson-g12a-usb-ctrl.yaml @@ -25,13 +25,14 @@ description: | The Amlogic A1 embeds a DWC3 USB IP Core configured for USB2 in host-only mode. - The Amlogic GXL & GXM SoCs doesn't embed an USB3 PHY. + The Amlogic GXL, GXM & AXG SoCs doesn't embed an USB3 PHY. properties: compatible: enum: - amlogic,meson-gxl-usb-ctrl - amlogic,meson-gxm-usb-ctrl + - amlogic,meson-axg-usb-ctrl - amlogic,meson-g12a-usb-ctrl - amlogic,meson-a1-usb-ctrl @@ -155,6 +156,25 @@ allOf: properties: compatible: enum: + - amlogic,meson-axg-usb-ctrl + + then: + properties: + phy-names: + items: + - const: usb2-phy1 # USB2 PHY1 if USBOTG_B port is used + clocks: + minItems: 2 + clock-names: + items: + - const: usb_ctrl + - const: ddr + required: + - clock-names + - if: + properties: + compatible: + enum: - amlogic,meson-a1-usb-ctrl then: diff --git a/Documentation/devicetree/bindings/usb/atmel-usb.txt b/Documentation/devicetree/bindings/usb/atmel-usb.txt index 423b99a8fd97..a4002624ba14 100644 --- a/Documentation/devicetree/bindings/usb/atmel-usb.txt +++ b/Documentation/devicetree/bindings/usb/atmel-usb.txt @@ -82,6 +82,7 @@ Required properties: "atmel,at91sam9rl-udc" "atmel,at91sam9g45-udc" "atmel,sama5d3-udc" + "microchip,sam9x60-udc" - reg: Address and length of the register set for the device - interrupts: Should contain usba interrupt - clocks: Should reference the peripheral and host clocks diff --git a/Documentation/devicetree/bindings/usb/cdns,usb3.yaml b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml new file mode 100644 index 000000000000..ac20b98e9910 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/cdns,usb3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence USBSS-DRD controller bindings + +maintainers: + - Pawel Laszczak <pawell@cadence.com> + +properties: + compatible: + const: cdns,usb3 + + reg: + items: + - description: OTG controller registers + - description: XHCI Host controller registers + - description: DEVICE controller registers + + reg-names: + items: + - const: otg + - const: xhci + - const: dev + + interrupts: + items: + - description: OTG/DRD controller interrupt + - description: XHCI host controller interrupt + - description: Device controller interrupt + + interrupt-names: + items: + - const: host + - const: peripheral + - const: otg + + dr_mode: + enum: [host, otg, peripheral] + + maximum-speed: + enum: [super-speed, high-speed, full-speed] + + phys: + minItems: 1 + maxItems: 2 + + phy-names: + minItems: 1 + maxItems: 2 + items: + anyOf: + - const: cdns3,usb2-phy + - const: cdns3,usb3-phy + + cdns,on-chip-buff-size: + description: + size of memory intended as internal memory for endpoints + buffers expressed in KB + $ref: /schemas/types.yaml#/definitions/uint32 + + cdns,phyrst-a-enable: + description: Enable resetting of PHY if Rx fail is detected + type: boolean + +required: + - compatible + - reg + - reg-names + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + bus { + #address-cells = <2>; + #size-cells = <2>; + + usb@6000000 { + compatible = "cdns,usb3"; + reg = <0x00 0x6000000 0x00 0x10000>, + <0x00 0x6010000 0x00 0x10000>, + <0x00 0x6020000 0x00 0x10000>; + reg-names = "otg", "xhci", "dev"; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host", "peripheral", "otg"; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/cdns-usb3.txt b/Documentation/devicetree/bindings/usb/cdns-usb3.txt deleted file mode 100644 index b7dc606d37b5..000000000000 --- a/Documentation/devicetree/bindings/usb/cdns-usb3.txt +++ /dev/null @@ -1,45 +0,0 @@ -Binding for the Cadence USBSS-DRD controller - -Required properties: - - reg: Physical base address and size of the controller's register areas. - Controller has 3 different regions: - - HOST registers area - - DEVICE registers area - - OTG/DRD registers area - - reg-names - register memory area names: - "xhci" - for HOST registers space - "dev" - for DEVICE registers space - "otg" - for OTG/DRD registers space - - compatible: Should contain: "cdns,usb3" - - interrupts: Interrupts used by cdns3 controller: - "host" - interrupt used by XHCI driver. - "peripheral" - interrupt used by device driver - "otg" - interrupt used by DRD/OTG part of driver - -Optional properties: - - maximum-speed : valid arguments are "super-speed", "high-speed" and - "full-speed"; refer to usb/generic.txt - - dr_mode: Should be one of "host", "peripheral" or "otg". - - phys: reference to the USB PHY - - phy-names: from the *Generic PHY* bindings; - Supported names are: - - cdns3,usb2-phy - - cdns3,usb3-phy - - - cdns,on-chip-buff-size : size of memory intended as internal memory for endpoints - buffers expressed in KB - -Example: - usb@f3000000 { - compatible = "cdns,usb3"; - interrupts = <GIC_USB_IRQ 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_USB_IRQ 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_USB_IRQ 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host", "peripheral", "otg"; - reg = <0xf3000000 0x10000>, /* memory area for HOST registers */ - <0xf3010000 0x10000>, /* memory area for DEVICE registers */ - <0xf3020000 0x10000>; /* memory area for OTG/DRD registers */ - reg-names = "xhci", "dev", "otg"; - phys = <&usb2_phy>, <&usb3_phy>; - phy-names = "cdns3,usb2-phy", "cnds3,usb3-phy"; - }; diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt index 51376cbe5f3d..a5c5db6a0b2d 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt @@ -100,6 +100,15 @@ i.mx specific properties It's recommended to specify the over current polarity. - power-active-high: power signal polarity is active high - external-vbus-divider: enables off-chip resistor divider for Vbus +- samsung,picophy-pre-emp-curr-control: HS Transmitter Pre-Emphasis Current + Control. This signal controls the amount of current sourced to the + USB_OTG*_DP and USB_OTG*_DN pins after a J-to-K or K-to-J transition. + The range is from 0x0 to 0x3, the default value is 0x1. + Details can refer to TXPREEMPAMPTUNE0 bits of USBNC_n_PHY_CFG1. +- samsung,picophy-dc-vol-level-adjust: HS DC Voltage Level Adjustment. + Adjust the high-speed transmitter DC level voltage. + The range is from 0x0 to 0xf, the default value is 0x3. + Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1. Example: diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml index ffa157a0fce7..e5ee51b7b470 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.yaml +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml @@ -39,6 +39,7 @@ properties: - amlogic,meson-g12a-usb - const: snps,dwc2 - const: amcc,dwc-otg + - const: apm,apm82181-dwc-otg - const: snps,dwc2 - const: st,stm32f4x9-fsotg - const: st,stm32f4x9-hsotg @@ -102,6 +103,10 @@ properties: dr_mode: enum: [host, peripheral, otg] + usb-role-switch: + $ref: /schemas/types.yaml#/definitions/flag + description: Support role switch. + g-rx-fifo-size: $ref: /schemas/types.yaml#/definitions/uint32 description: size of rx fifo size in gadget mode. diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index d03edf9d3935..1aae2b6160c1 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -78,6 +78,9 @@ Optional properties: park mode are disabled. - snps,dis_metastability_quirk: when set, disable metastability workaround. CAUTION: use only if you are absolutely sure of it. + - snps,dis-split-quirk: when set, change the way URBs are handled by the + driver. Needed to avoid -EPROTO errors with usbhid + on some devices (Hikey 970). - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal utmi_l1_suspend_n, false when asserts utmi_sleep_n - snps,hird-threshold: HIRD threshold diff --git a/Documentation/devicetree/bindings/usb/intel,keembay-dwc3.yaml b/Documentation/devicetree/bindings/usb/intel,keembay-dwc3.yaml new file mode 100644 index 000000000000..dd32c10ce6c7 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/intel,keembay-dwc3.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/intel,keembay-dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay DWC3 USB controller + +maintainers: + - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> + +properties: + compatible: + const: intel,keembay-dwc3 + + clocks: + maxItems: 4 + + clock-names: + items: + - const: async_master + - const: ref + - const: alt_ref + - const: suspend + + ranges: true + + '#address-cells': + enum: [ 1, 2 ] + + '#size-cells': + enum: [ 1, 2 ] + +# Required child node: + +patternProperties: + "^dwc3@[0-9a-f]+$": + type: object + description: + A child node must exist to represent the core DWC3 IP block. + The content of the node is defined in dwc3.txt. + +required: + - compatible + - clocks + - clock-names + - ranges + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #define KEEM_BAY_A53_AUX_USB + #define KEEM_BAY_A53_AUX_USB_REF + #define KEEM_BAY_A53_AUX_USB_ALT_REF + #define KEEM_BAY_A53_AUX_USB_SUSPEND + + usb { + compatible = "intel,keembay-dwc3"; + clocks = <&scmi_clk KEEM_BAY_A53_AUX_USB>, + <&scmi_clk KEEM_BAY_A53_AUX_USB_REF>, + <&scmi_clk KEEM_BAY_A53_AUX_USB_ALT_REF>, + <&scmi_clk KEEM_BAY_A53_AUX_USB_SUSPEND>; + clock-names = "async_master", "ref", "alt_ref", "suspend"; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + dwc3@34000000 { + compatible = "snps,dwc3"; + reg = <0x34000000 0x10000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "peripheral"; + }; + }; diff --git a/Documentation/devicetree/bindings/usb/mediatek,mt6360-tcpc.yaml b/Documentation/devicetree/bindings/usb/mediatek,mt6360-tcpc.yaml new file mode 100644 index 000000000000..1e8e1c22180e --- /dev/null +++ b/Documentation/devicetree/bindings/usb/mediatek,mt6360-tcpc.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/usb/mediatek,mt6360-tcpc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Mediatek MT6360 Type-C Port Switch and Power Delivery controller DT bindings + +maintainers: + - ChiYuan Huang <cy_huang@richtek.com> + +description: | + Mediatek MT6360 is a multi-functional device. It integrates charger, ADC, flash, RGB indicators, + regulators (BUCKs/LDOs), and TypeC Port Switch with Power Delivery controller. + This document only describes MT6360 Type-C Port Switch and Power Delivery controller. + +properties: + compatible: + enum: + - mediatek,mt6360-tcpc + + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: PD_IRQB + + connector: + type: object + $ref: ../connector/usb-connector.yaml# + description: + Properties for usb c connector. + +additionalProperties: false + +required: + - compatible + - interrupts + - interrupt-names + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/usb/pd.h> + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + mt6360@34 { + compatible = "mediatek,mt6360"; + reg = <0x34>; + tcpc { + compatible = "mediatek,mt6360-tcpc"; + interrupts-extended = <&gpio26 3 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "PD_IRQB"; + + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + data-role = "dual"; + power-role = "dual"; + try-power-role = "sink"; + source-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>; + sink-pdos = <PDO_FIXED(5000, 2000, PDO_FIXED_DUAL_ROLE | PDO_FIXED_DATA_SWAP)>; + op-sink-microwatt = <10000000>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&usb_hs>; + }; + }; + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&usb_ss>; + }; + }; + port@2 { + reg = <2>; + endpoint { + remote-endpoint = <&dp_aux>; + }; + }; + }; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/usb/renesas,usb-xhci.yaml b/Documentation/devicetree/bindings/usb/renesas,usb-xhci.yaml index add9f7b66da0..0f078bd0a3e5 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usb-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usb-xhci.yaml @@ -30,6 +30,7 @@ properties: - renesas,xhci-r8a774a1 # RZ/G2M - renesas,xhci-r8a774b1 # RZ/G2N - renesas,xhci-r8a774c0 # RZ/G2E + - renesas,xhci-r8a774e1 # RZ/G2H - renesas,xhci-r8a7795 # R-Car H3 - renesas,xhci-r8a7796 # R-Car M3-W - renesas,xhci-r8a77961 # R-Car M3-W+ diff --git a/Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml b/Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml index e3cdeab1199f..929a3f413b44 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usb3-peri.yaml @@ -16,6 +16,7 @@ properties: - renesas,r8a774a1-usb3-peri # RZ/G2M - renesas,r8a774b1-usb3-peri # RZ/G2N - renesas,r8a774c0-usb3-peri # RZ/G2E + - renesas,r8a774e1-usb3-peri # RZ/G2H - renesas,r8a7795-usb3-peri # R-Car H3 - renesas,r8a7796-usb3-peri # R-Car M3-W - renesas,r8a77961-usb3-peri # R-Car M3-W+ @@ -52,11 +53,24 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle description: phandle of a companion. - port: + ports: description: | any connector to the data bus of this controller should be modelled using the OF graph bindings specified, if the "usb-role-switch" property is used. + type: object + properties: + port@0: + type: object + description: High Speed (HS) data bus. + + port@1: + type: object + description: Super Speed (SS) data bus. + + required: + - port@0 + - port@1 required: - compatible @@ -79,9 +93,20 @@ examples: companion = <&xhci0>; usb-role-switch; - port { - usb3_role_switch: endpoint { - remote-endpoint = <&hd3ss3220_ep>; - }; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + usb3_hs_ep: endpoint { + remote-endpoint = <&hs_ep>; + }; + }; + port@1 { + reg = <1>; + usb3_role_switch: endpoint { + remote-endpoint = <&hd3ss3220_out_ep>; + }; + }; }; }; diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml index af4826fb6824..737c1f47b7de 100644 --- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml +++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml @@ -39,6 +39,7 @@ properties: - renesas,usbhs-r8a774a1 # RZ/G2M - renesas,usbhs-r8a774b1 # RZ/G2N - renesas,usbhs-r8a774c0 # RZ/G2E + - renesas,usbhs-r8a774e1 # RZ/G2H - renesas,usbhs-r8a7795 # R-Car H3 - renesas,usbhs-r8a7796 # R-Car M3-W - renesas,usbhs-r8a77961 # R-Car M3-W+ diff --git a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt b/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt deleted file mode 100644 index 2bd21b22ce95..000000000000 --- a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.txt +++ /dev/null @@ -1,38 +0,0 @@ -TI HD3SS3220 TypeC DRP Port Controller. - -Required properties: - - compatible: Must be "ti,hd3ss3220". - - reg: I2C slave address, must be 0x47 or 0x67 based on ADDR pin. - - interrupts: An interrupt specifier. - -Required sub-node: - - connector: The "usb-c-connector" attached to the hd3ss3220 chip. The - bindings of the connector node are specified in: - - Documentation/devicetree/bindings/connector/usb-connector.yaml - -Example: -hd3ss3220@47 { - compatible = "ti,hd3ss3220"; - reg = <0x47>; - interrupt-parent = <&gpio6>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - hd3ss3220_ep: endpoint { - remote-endpoint = <&usb3_role_switch>; - }; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml b/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml new file mode 100644 index 000000000000..5fe9e6211ba2 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/ti,hd3ss3220.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI HD3SS3220 TypeC DRP Port Controller + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + +description: |- + HD3SS3220 is a USB SuperSpeed (SS) 2:1 mux with DRP port controller. The device provides Channel + Configuration (CC) logic and 5V VCONN sourcing for ecosystems implementing USB Type-C. The + HD3SS3220 can be configured as a Downstream Facing Port (DFP), Upstream Facing Port (UFP) or a + Dual Role Port (DRP) making it ideal for any application. + +properties: + compatible: + const: ti,hd3ss3220 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ports: + description: OF graph bindings (specified in bindings/graph.txt) that model + SS data bus to the SS capable connector. + type: object + properties: + port@0: + type: object + description: Super Speed (SS) MUX inputs connected to SS capable connector. + $ref: /connector/usb-connector.yaml#/properties/ports/properties/port@1 + + port@1: + type: object + description: Output of 2:1 MUX connected to Super Speed (SS) data bus. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + hd3ss3220@47 { + compatible = "ti,hd3ss3220"; + reg = <0x47>; + interrupt-parent = <&gpio6>; + interrupts = <3>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + hd3ss3220_in_ep: endpoint { + remote-endpoint = <&ss_ep>; + }; + }; + port@1 { + reg = <1>; + hd3ss3220_out_ep: endpoint { + remote-endpoint = <&usb3_role_switch>; + }; + }; + }; + }; + }; |