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authorLinus Torvalds2018-08-14 12:01:08 -0700
committerLinus Torvalds2018-08-14 12:01:08 -0700
commit010b0e708e08727d38b82accb21832b63fe2c250 (patch)
tree29f110982a25675c02346320b2529ffd82aef244 /Documentation
parent792adb90fa724ce07c0171cbc96b9215af4b1045 (diff)
parentc1acb21b32a3bb601453764c9eac9fc8fbb3a81d (diff)
Merge tag 'spi-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi updates from Mark Brown: "Quite an active release for the SPI subsystem, lots of small updates and fixes scattered about with highlights including: - 3-wire support in the GPIO driver. - support for setting a custom memory name in the memory mapped flash drivers. - support for extended mode in the Freescale DSPI controller. - support for the non-standard integration with the Microsemi Ocelot platform in the DesignWare driver. - new driver for the SocioNext UniPhier" * tag 'spi-v4.19' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (47 commits) spi: davinci: fix a NULL pointer dereference spi: spi-mem: Constify spi_mem->name mtd: m25p80: Call spi_mem_get_name() to let controller set a custom name spi: spi-mem: Extend the SPI mem interface to set a custom memory name spi: spi-mem: Fix a typo in the documentation of struct spi_mem spi: uniphier: remove unnecessary include headers spi: spi-gpio: add SPI_3WIRE support spi: add flags parameter to txrx_word function pointers spi: add SPI controller driver for UniPhier SoC spi: add DT bindings for UniPhier SPI controller spi: dw: document Microsemi integration spi: img-spfi: Set device select bits for SPFI port state spi: omap2-mcspi: remove several redundant variables spi: dw-mmio: add MSCC Ocelot support spi: dw: export dw_spi_set_cs spi: spi-fsl-espi: Log fifo counters on error spi: imx: Use the longuest possible burst size when in dynamic_burst spi: imx: remove unnecessary check in spi_imx_can_dma spi: imx: Use correct number of bytes per words spi: imx: Use dynamic bursts only when bits_per_word is 8, 16 or 32 ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt6
-rw-r--r--Documentation/devicetree/bindings/spi/spi-rockchip.txt1
-rw-r--r--Documentation/devicetree/bindings/spi/spi-uniphier.txt22
3 files changed, 27 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
index 204b311e0400..642d3fb1ef85 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
@@ -1,8 +1,10 @@
Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
Required properties:
-- compatible : "snps,dw-apb-ssi"
-- reg : The register base for the controller.
+- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
+ "jaguar2"
+- reg : The register base for the controller. For "mscc,<soc>-spi", a second
+ register set is required (named ICPU_CFG:SPI_MST)
- interrupts : One interrupt, used by the controller.
- #address-cells : <1>, as required by generic SPI binding.
- #size-cells : <0>, also as required by generic SPI binding.
diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
index 6e3ffacbba32..a0edac12d8df 100644
--- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt
+++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
@@ -7,6 +7,7 @@ Required Properties:
- compatible: should be one of the following.
"rockchip,rv1108-spi" for rv1108 SoCs.
+ "rockchip,px30-spi", "rockchip,rk3066-spi" for px30 SoCs.
"rockchip,rk3036-spi" for rk3036 SoCS.
"rockchip,rk3066-spi" for rk3066 SoCs.
"rockchip,rk3188-spi" for rk3188 SoCs.
diff --git a/Documentation/devicetree/bindings/spi/spi-uniphier.txt b/Documentation/devicetree/bindings/spi/spi-uniphier.txt
new file mode 100644
index 000000000000..504a4ecfc7b1
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-uniphier.txt
@@ -0,0 +1,22 @@
+Socionext UniPhier SPI controller driver
+
+UniPhier SoCs have SCSSI which supports SPI single channel.
+
+Required properties:
+ - compatible: should be "socionext,uniphier-scssi"
+ - reg: address and length of the spi master registers
+ - #address-cells: must be <1>, see spi-bus.txt
+ - #size-cells: must be <0>, see spi-bus.txt
+ - clocks: A phandle to the clock for the device.
+ - resets: A phandle to the reset control for the device.
+
+Example:
+
+spi0: spi@54006000 {
+ compatible = "socionext,uniphier-scssi";
+ reg = <0x54006000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&peri_clk 11>;
+ resets = <&peri_rst 11>;
+};