diff options
| author | Lubomir Rintel | 2020-03-17 10:39:08 +0100 |
|---|---|---|
| committer | Rob Herring | 2020-03-31 09:03:33 -0600 |
| commit | 39648d052f842d0f6c95dacdeb6317f27b9e71f9 (patch) | |
| tree | ddb89dd4c8433c92152eaca0d272e368aa42566a /Documentation | |
| parent | 7f464532b05dadc8f96acdda7093334c863e7a06 (diff) | |
dt-bindings: arm: l2x0: Tauros 3 is PL310 compatible
The validation is unhappy about mmp3-dell-ariel declaring its
marvell,tauros3-cache node to be compatible with arm,pl310-cache:
mmp3-dell-ariel.dt.yaml: cache-controller@d0020000: compatible:
Additional items are not allowed ('arm,pl310-cache' was unexpected)
mmp3-dell-ariel.dt.yaml: cache-controller@d0020000: compatible:
['marvell,tauros3-cache', 'arm,pl310-cache'] is too long
Let's allow this -- Tauros 3 is designed to be compatible with PL310.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
[robh: fixup indentation]
Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/arm/l2c2x0.yaml | 45 |
1 files changed, 24 insertions, 21 deletions
diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.yaml b/Documentation/devicetree/bindings/arm/l2c2x0.yaml index 913a8cd8b2c0..5d1d50eea26e 100644 --- a/Documentation/devicetree/bindings/arm/l2c2x0.yaml +++ b/Documentation/devicetree/bindings/arm/l2c2x0.yaml @@ -29,27 +29,30 @@ allOf: properties: compatible: - enum: - - arm,pl310-cache - - arm,l220-cache - - arm,l210-cache - # DEPRECATED by "brcm,bcm11351-a2-pl310-cache" - - bcm,bcm11351-a2-pl310-cache - # For Broadcom bcm11351 chipset where an - # offset needs to be added to the address before passing down to the L2 - # cache controller - - brcm,bcm11351-a2-pl310-cache - # Marvell Controller designed to be - # compatible with the ARM one, with system cache mode (meaning - # maintenance operations on L1 are broadcasted to the L2 and L2 - # performs the same operation). - - marvell,aurora-system-cache - # Marvell Controller designed to be - # compatible with the ARM one with outer cache mode. - - marvell,aurora-outer-cache - # Marvell Tauros3 cache controller, compatible - # with arm,pl310-cache controller. - - marvell,tauros3-cache + oneOf: + - enum: + - arm,pl310-cache + - arm,l220-cache + - arm,l210-cache + # DEPRECATED by "brcm,bcm11351-a2-pl310-cache" + - bcm,bcm11351-a2-pl310-cache + # For Broadcom bcm11351 chipset where an + # offset needs to be added to the address before passing down to the L2 + # cache controller + - brcm,bcm11351-a2-pl310-cache + # Marvell Controller designed to be + # compatible with the ARM one, with system cache mode (meaning + # maintenance operations on L1 are broadcasted to the L2 and L2 + # performs the same operation). + - marvell,aurora-system-cache + # Marvell Controller designed to be + # compatible with the ARM one with outer cache mode. + - marvell,aurora-outer-cache + - items: + # Marvell Tauros3 cache controller, compatible + # with arm,pl310-cache controller. + - const: marvell,tauros3-cache + - const: arm,pl310-cache cache-level: const: 2 |