diff options
| author | Deepak Sharma | 2021-09-23 23:12:05 -0700 |
|---|---|---|
| committer | Rafael J. Wysocki | 2021-10-01 20:44:31 +0200 |
| commit | a8fb40966f19ff81520d9ccf8f7e2b95201368b8 (patch) | |
| tree | 5b649fac13f7a86f9d6e64d3320d20678bc39863 /MAINTAINERS | |
| parent | aa06e20f1be628186f0c2dcec09ea0009eb69778 (diff) | |
x86: ACPI: cstate: Optimize C3 entry on AMD CPUs
All Zen or newer CPU which support C3 shares cache. Its not necessary to
flush the caches in software before entering C3. This will cause drop in
performance for the cores which share some caches. ARB_DIS is not used
with current AMD C state implementation. So set related flags correctly.
Signed-off-by: Deepak Sharma <deepak.sharma@amd.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat (limited to 'MAINTAINERS')
0 files changed, 0 insertions, 0 deletions