diff options
| author | Eugeniy Paltsev | 2017-12-09 16:59:15 +0300 |
|---|---|---|
| committer | Vineet Gupta | 2017-12-20 12:41:44 -0800 |
| commit | a08c832f277d7a6f9d3b341a5d5df2f5576220d8 (patch) | |
| tree | 904c7baed42e96d959eaaa26c943abf4b95ee0c8 /arch/arc/boot/dts | |
| parent | c18fc9071762769acb4040cabae45c817aefc537 (diff) | |
ARC: [plat-hsdk]: Set initial core pll output frequency
Set initial core pll output frequency specified in device tree to
1GHz. It will be applied at the core pll driver probing.
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/boot/dts')
| -rw-r--r-- | arch/arc/boot/dts/hsdk.dts | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts index 8f627c200d60..006aa3de5348 100644 --- a/arch/arc/boot/dts/hsdk.dts +++ b/arch/arc/boot/dts/hsdk.dts @@ -114,6 +114,14 @@ reg = <0x00 0x10>, <0x14B8 0x4>; #clock-cells = <0>; clocks = <&input_clk>; + + /* + * Set initial core pll output frequency to 1GHz. + * It will be applied at the core pll driver probing + * on early boot. + */ + assigned-clocks = <&core_clk>; + assigned-clock-rates = <1000000000>; }; serial: serial@5000 { |