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authorVineet Gupta2015-06-04 14:39:15 +0530
committerVineet Gupta2015-06-22 14:06:56 +0530
commitbcc4d65abec2adb74157b34519e80331eb4427eb (patch)
treebb35ec4fc31cc6f9e8d3063c82cf682e2e723434 /arch/arc/mm/cache.c
parentd1f317d8254413447bcd6b6adbde24a985d256c2 (diff)
ARCv2: MMUv4: support aliasing icache config
This is also default for AXS103 release Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/mm/cache.c')
-rw-r--r--arch/arc/mm/cache.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 7a898f57d84b..0eaaee60fd0b 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -21,6 +21,9 @@
#include <asm/cachectl.h>
#include <asm/setup.h>
+void (*_cache_line_loop_ic_fn)(unsigned long paddr, unsigned long vaddr,
+ unsigned long sz, const int cacheop);
+
char *arc_cache_mumbojumbo(int c, char *buf, int len)
{
int n = 0;
@@ -414,7 +417,7 @@ __ic_line_inv_vaddr_local(unsigned long paddr, unsigned long vaddr,
unsigned long flags;
local_irq_save(flags);
- __cache_line_loop(paddr, vaddr, sz, OP_INV_IC);
+ (*_cache_line_loop_ic_fn)(paddr, vaddr, sz, OP_INV_IC);
local_irq_restore(flags);
}
@@ -746,6 +749,15 @@ void arc_cache_init(void)
if (ic->ver != CONFIG_ARC_MMU_VER)
panic("Cache ver [%d] doesn't match MMU ver [%d]\n",
ic->ver, CONFIG_ARC_MMU_VER);
+
+ /*
+ * In MMU v4 (HS38x) the alising icache config uses IVIL/PTAG
+ * pair to provide vaddr/paddr respectively, just as in MMU v3
+ */
+ if (is_isa_arcv2() && ic->alias)
+ _cache_line_loop_ic_fn = __cache_line_loop_v3;
+ else
+ _cache_line_loop_ic_fn = __cache_line_loop;
}
if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) {