diff options
| author | Vineet Gupta | 2016-04-05 19:32:32 +0530 |
|---|---|---|
| committer | Vineet Gupta | 2016-05-09 09:32:28 +0530 |
| commit | 0eeb3dfe4b85aa7367e5e4efc365abbe4e50bbfa (patch) | |
| tree | 0c26f9b2788325aa8d1f9987b957d83d7a41b5a3 /arch/arc/plat-axs10x | |
| parent | 569579401ae1c9b9f317f38261e32135b153e9b3 (diff) | |
ARC: [plat-axs] Refactor core freq get/set
Reduces diff in future patches !
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/plat-axs10x')
| -rw-r--r-- | arch/arc/plat-axs10x/axs10x.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c index 1b0f0f458a2b..8e7f50a8b857 100644 --- a/arch/arc/plat-axs10x/axs10x.c +++ b/arch/arc/plat-axs10x/axs10x.c @@ -389,6 +389,8 @@ axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od) static void __init axs103_early_init(void) { + u32 freq = arc_get_core_freq(), orig = freq; + /* * AXS103 configurations for SMP/QUAD configurations share device tree * which defaults to 90 MHz. However recent failures of Quad config @@ -401,12 +403,12 @@ static void __init axs103_early_init(void) #ifdef CONFIG_ARC_MCIP unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F; if (num_cores > 2) - arc_set_core_freq(50 * 1000000); + freq = 50; else if (num_cores == 2) - arc_set_core_freq(75 * 1000000); + freq = 75; #endif - switch (arc_get_core_freq()/1000000) { + switch (freq) { case 33: axs103_set_freq(1, 1, 1); break; @@ -431,11 +433,14 @@ static void __init axs103_early_init(void) * DT "clock-frequency" might not match with board value. * Hence update it to match the board value. */ - arc_set_core_freq(axs103_get_freq() * 1000000); + freq = axs103_get_freq(); break; } - pr_info("Freq is %dMHz\n", axs103_get_freq()); + pr_info("Freq is %dMHz\n", freq); + if (freq != orig ) { + arc_set_core_freq(freq * 1000000); + } /* Memory maps already config in pre-bootloader */ |