diff options
| author | Noam Camus | 2016-11-16 08:31:11 +0200 |
|---|---|---|
| committer | Vineet Gupta | 2016-11-30 11:54:25 -0800 |
| commit | 09dcd1958be42ea473fef24a2c02d975f520ea71 (patch) | |
| tree | 60d945f93dc3796e85e7cb37b06039e91a806199 /arch/arc | |
| parent | c4c9a040ecb7297e011e579f5a9cc280e42d725f (diff) | |
soc: Support for NPS HW scheduling
This new header file is for NPS400 SoC (part of ARC architecture).
The header file includes macros for save/restore of HW scheduling.
The control of HW scheduling is achieved by writing core registers.
This code was moved from arc/plat-eznps so it can be used
from drivers/clocksource/, available only for CONFIG_EZNPS_MTM_EXT.
Signed-off-by: Noam Camus <noamca@mellanox.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'arch/arc')
| -rw-r--r-- | arch/arc/plat-eznps/include/plat/ctop.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h index 9d6718c1a199..ee2e32df5e90 100644 --- a/arch/arc/plat-eznps/include/plat/ctop.h +++ b/arch/arc/plat-eznps/include/plat/ctop.h @@ -46,9 +46,7 @@ #define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300) /* EZchip core instructions */ -#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF #define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF -#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3 #define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103 #define CTOP_INST_SCHD_RW 0x3E6F7004 #define CTOP_INST_SCHD_RD 0x3E6F7084 |