diff options
| author | Geert Uytterhoeven | 2015-11-23 14:56:00 +0100 |
|---|---|---|
| committer | Simon Horman | 2015-11-25 10:42:38 +0900 |
| commit | c8d9fdbe2d648caaa510d45dc13eba2e9957140b (patch) | |
| tree | 5ffdb3d00330f7df26039f04c4155b3f6ba4b69c /arch/arm/boot/dts/sh73a0.dtsi | |
| parent | 374e70075e58acfe922869aad1202b29f8fb76f5 (diff) | |
ARM: shmobile: sh73a0 dtsi: Add L2 cache-controller node
Add the missing L2 cache-controller node, and link the CPU nodes to it.
This will allow migration to the generic l2c OF initialization.
The L2 cache is an ARM L2C-310 (r3p1), of size 512 KiB (64 KiB x 8
ways).
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/sh73a0.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/sh73a0.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi index ff7c8f298f30..319551f0fcdb 100644 --- a/arch/arm/boot/dts/sh73a0.dtsi +++ b/arch/arm/boot/dts/sh73a0.dtsi @@ -28,6 +28,7 @@ reg = <0>; clock-frequency = <1196000000>; power-domains = <&pd_a2sl>; + next-level-cache = <&L2>; }; cpu@1 { device_type = "cpu"; @@ -35,6 +36,7 @@ reg = <1>; clock-frequency = <1196000000>; power-domains = <&pd_a2sl>; + next-level-cache = <&L2>; }; }; @@ -53,6 +55,18 @@ <0xf0000100 0x100>; }; + L2: cache-controller { + compatible = "arm,pl310-cache"; + reg = <0xf0100000 0x1000>; + interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd_a3sm>; + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + arm,shared-override; + cache-unified; + cache-level = <2>; + }; + sbsc2: memory-controller@fb400000 { compatible = "renesas,sbsc-sh73a0"; reg = <0xfb400000 0x400>; |