diff options
| author | Venu Byravarasu | 2013-05-16 19:42:56 +0530 |
|---|---|---|
| committer | Stephen Warren | 2013-05-17 16:22:05 -0600 |
| commit | 9dffe3be3f321581c4510f2fa2e217b18c703bcd (patch) | |
| tree | 671d71489dad5f1d1868f68a6eee654be4fa16d9 /arch/arm/boot/dts/tegra20-seaboard.dts | |
| parent | d400f209b4afe4a196baac276128eccac6a11b31 (diff) | |
ARM: tegra: modify ULPI reset GPIO properties
1. All Tegra20 ULPI reset GPIO DT properties are modified to indicate active
low nature of the GPIO.
2. Placed USB PHY DT node immediately below the EHCI controller DT nodes
and corrected reg value in the name of USB PHY DT node.
Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat (limited to 'arch/arm/boot/dts/tegra20-seaboard.dts')
| -rw-r--r-- | arch/arm/boot/dts/tegra20-seaboard.dts | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index cee4c34010fe..9dd4f8ee4f4a 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -571,15 +571,15 @@ usb@c5004000 { status = "okay"; - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ }; - usb@c5008000 { - status = "okay"; + usb-phy@c5004000 { + nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */ }; - usb-phy@c5004400 { - nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */ + usb@c5008000 { + status = "okay"; }; sdhci@c8000000 { |