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authorArnd Bergmann2017-12-21 17:19:38 +0100
committerArnd Bergmann2017-12-21 17:19:38 +0100
commit24ff73a0af2c41fa32fd5d0836ab52e7cc93e9d5 (patch)
treed0af0cd2896b7562bcdbde188f438f0d84878aba /arch/arm/boot
parent8d7ac420c161a63574e1709288a035148d3b377e (diff)
parent80a06c0d8357d1e75a8fbc10813fcdada4d897fb (diff)
Merge tag 'omap-for-v4.16/dt-clk-signed' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Pull "Clock related dts changes for omaps for v4.16 merge window" from Tony Lindgren: This branch contains a series of dts changes from Tero Kristo to start using clkctrl clocks. Note that this branch is based on a merge of omap-for-v4.16/soc-signed and an immutable commit from Tero Kristo fe7020e64f04 ("clk: ti: omap4: clkctrl data fixes for opt-clocks") that is also in clk-next. * tag 'omap-for-v4.16/dt-clk-signed' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (57 commits) ARM: dts: dm816x: add clkctrl nodes ARM: dts: dm814x: add clkctrl nodes ARM: dts: am43xx: add clkctrl nodes ARM: dts: am33xx: add clkctrl nodes ARM: dts: dra7: add clkctrl nodes ARM: dts: omap5: add clkctrl nodes ARM: dts: omap4: add clkctrl nodes ARM: dts: dm816x: add bus functionality to base PRCM node ARM: dts: am43xx: add bus functionality to base PRCM node ARM: dts: am33xx: add bus functionality to base PRCM node ARM: dts: dra7: add bus functionality to base PRCM nodes ARM: dts: omap4: add bus functionality to base PRCM nodes ARM: dts: omap5: add bus functionality to base PRCM nodes ARM: dts: dm816x: add fck under timers1/2 ARM: dts: dm814x: add fck under timers1/2 ARM: dts: dra7: add fck under timer1 ARM: dts: am43xx: add fck under timers1/2 ARM: dts: am33xx: add fck under timers1/2 ARM: dts: omap4: add fck under timer1 ARM: dts: omap5: add fck under timer1 ...
Diffstat (limited to 'arch/arm/boot')
-rw-r--r--arch/arm/boot/dts/am335x-bone-common.dtsi2
-rw-r--r--arch/arm/boot/dts/am335x-boneblue.dts2
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts2
-rw-r--r--arch/arm/boot/dts/am335x-evmsk.dts2
-rw-r--r--arch/arm/boot/dts/am33xx-clocks.dtsi205
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi14
-rw-r--r--arch/arm/boot/dts/am4372.dtsi16
-rw-r--r--arch/arm/boot/dts/am43x-epos-evm.dts2
-rw-r--r--arch/arm/boot/dts/am43xx-clocks.dtsi230
-rw-r--r--arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi2
-rw-r--r--arch/arm/boot/dts/dm814x-clocks.dtsi30
-rw-r--r--arch/arm/boot/dts/dm814x.dtsi4
-rw-r--r--arch/arm/boot/dts/dm816x-clocks.dtsi30
-rw-r--r--arch/arm/boot/dts/dm816x.dtsi9
-rw-r--r--arch/arm/boot/dts/dra7-evm-common.dtsi4
-rw-r--r--arch/arm/boot/dts/dra7.dtsi84
-rw-r--r--arch/arm/boot/dts/dra72-evm-common.dtsi4
-rw-r--r--arch/arm/boot/dts/dra72x.dtsi4
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi6
-rw-r--r--arch/arm/boot/dts/dra7xx-clocks.dtsi909
-rw-r--r--arch/arm/boot/dts/omap4.dtsi37
-rw-r--r--arch/arm/boot/dts/omap44xx-clocks.dtsi895
-rw-r--r--arch/arm/boot/dts/omap5.dtsi46
-rw-r--r--arch/arm/boot/dts/omap54xx-clocks.dtsi623
24 files changed, 1091 insertions, 2071 deletions
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 48a15fc641f2..e67b4d65c8d0 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -409,6 +409,6 @@
};
&rtc {
- clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
diff --git a/arch/arm/boot/dts/am335x-boneblue.dts b/arch/arm/boot/dts/am335x-boneblue.dts
index cdc1b2be792f..d5be9fc4f416 100644
--- a/arch/arm/boot/dts/am335x-boneblue.dts
+++ b/arch/arm/boot/dts/am335x-boneblue.dts
@@ -446,7 +446,7 @@
&rtc {
system-power-controller;
- clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index ddd897556e03..fee6b3ee1741 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -790,6 +790,6 @@
};
&rtc {
- clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 9ba4b18c0cb2..fa608cd5dc14 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -722,6 +722,6 @@
};
&rtc {
- clocks = <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clocks = <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "ext-clk", "int-clk";
};
diff --git a/arch/arm/boot/dts/am33xx-clocks.dtsi b/arch/arm/boot/dts/am33xx-clocks.dtsi
index 8d8319590cde..95d5c9d136c5 100644
--- a/arch/arm/boot/dts/am33xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am33xx-clocks.dtsi
@@ -292,14 +292,6 @@
clock-div = <4>;
};
- cefuse_fck: cefuse_fck@a20 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_clkin_ck>;
- ti,bit-shift = <1>;
- reg = <0x0a20>;
- };
-
clk_24mhz: clk_24mhz {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -316,14 +308,6 @@
clock-div = <732>;
};
- clkdiv32k_ick: clkdiv32k_ick@14c {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ck>;
- ti,bit-shift = <1>;
- reg = <0x014c>;
- };
-
l3_gclk: l3_gclk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -350,49 +334,49 @@
timer1_fck: timer1_fck@528 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
+ clocks = <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
reg = <0x0528>;
};
timer2_fck: timer2_fck@508 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0508>;
};
timer3_fck: timer3_fck@50c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x050c>;
};
timer4_fck: timer4_fck@510 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0510>;
};
timer5_fck: timer5_fck@518 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0518>;
};
timer6_fck: timer6_fck@51c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x051c>;
};
timer7_fck: timer7_fck@504 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
+ clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0504>;
};
@@ -423,7 +407,7 @@
wdt1_fck: wdt1_fck@538 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
+ clocks = <&clk_rc32k_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x0538>;
};
@@ -493,42 +477,10 @@
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck@53c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
- clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
+ clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
reg = <0x053c>;
};
- gpio0_dbclk: gpio0_dbclk@408 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&gpio0_dbclk_mux_ck>;
- ti,bit-shift = <18>;
- reg = <0x0408>;
- };
-
- gpio1_dbclk: gpio1_dbclk@ac {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ick>;
- ti,bit-shift = <18>;
- reg = <0x00ac>;
- };
-
- gpio2_dbclk: gpio2_dbclk@b0 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ick>;
- ti,bit-shift = <18>;
- reg = <0x00b0>;
- };
-
- gpio3_dbclk: gpio3_dbclk@b4 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ick>;
- ti,bit-shift = <18>;
- reg = <0x00b4>;
- };
-
lcd_gclk: lcd_gclk@534 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -577,58 +529,6 @@
reg = <0x0700>;
};
- dbg_sysclk_ck: dbg_sysclk_ck@414 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_clkin_ck>;
- ti,bit-shift = <19>;
- reg = <0x0414>;
- };
-
- dbg_clka_ck: dbg_clka_ck@414 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_core_m4_ck>;
- ti,bit-shift = <30>;
- reg = <0x0414>;
- };
-
- stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck@414 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
- ti,bit-shift = <22>;
- reg = <0x0414>;
- };
-
- trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck@414 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
- ti,bit-shift = <20>;
- reg = <0x0414>;
- };
-
- stm_clk_div_ck: stm_clk_div_ck@414 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&stm_pmd_clock_mux_ck>;
- ti,bit-shift = <27>;
- ti,max-div = <64>;
- reg = <0x0414>;
- ti,index-power-of-two;
- };
-
- trace_clk_div_ck: trace_clk_div_ck@414 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&trace_pmd_clk_mux_ck>;
- ti,bit-shift = <24>;
- ti,max-div = <64>;
- reg = <0x0414>;
- ti,index-power-of-two;
- };
-
clkout2_ck: clkout2_ck@700 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -638,9 +538,88 @@
};
};
-&prcm_clockdomains {
- clk_24mhz_clkdm: clk_24mhz_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&clkdiv32k_ick>;
+&prcm {
+ l4_per_cm: l4_per_cm@0 {
+ compatible = "ti,omap4-cm";
+ reg = <0x0 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x200>;
+
+ l4_per_clkctrl: clk@14 {
+ compatible = "ti,clkctrl";
+ reg = <0x14 0x13c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_wkup_cm: l4_wkup_cm@400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x400 0x100>;
+
+ l4_wkup_clkctrl: clk@4 {
+ compatible = "ti,clkctrl";
+ reg = <0x4 0xd4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ mpu_cm: mpu_cm@600 {
+ compatible = "ti,omap4-cm";
+ reg = <0x600 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x600 0x100>;
+
+ mpu_clkctrl: clk@4 {
+ compatible = "ti,clkctrl";
+ reg = <0x4 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_rtc_cm: l4_rtc_cm@800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x800 0x100>;
+
+ l4_rtc_clkctrl: clk@0 {
+ compatible = "ti,clkctrl";
+ reg = <0x0 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ gfx_l3_cm: gfx_l3_cm@900 {
+ compatible = "ti,omap4-cm";
+ reg = <0x900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x900 0x100>;
+
+ gfx_l3_clkctrl: clk@4 {
+ compatible = "ti,clkctrl";
+ reg = <0x4 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_cefuse_cm: l4_cefuse_cm@a00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xa00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa00 0x100>;
+
+ l4_cefuse_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
};
};
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index d37f95025807..ca7400c20ed4 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/am33xx.h>
+#include <dt-bindings/clock/am3.h>
/ {
compatible = "ti,am33xx";
@@ -179,8 +180,11 @@
};
prcm: prcm@200000 {
- compatible = "ti,am3-prcm";
+ compatible = "ti,am3-prcm", "simple-bus";
reg = <0x200000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x200000 0x4000>;
prcm_clocks: clocks {
#address-cells = <1>;
@@ -517,6 +521,8 @@
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
+ clocks = <&timer1_fck>;
+ clock-names = "fck";
};
timer2: timer@48040000 {
@@ -524,6 +530,8 @@
reg = <0x48040000 0x400>;
interrupts = <68>;
ti,hwmods = "timer2";
+ clocks = <&timer2_fck>;
+ clock-names = "fck";
};
timer3: timer@48042000 {
@@ -571,7 +579,7 @@
interrupts = <75
76>;
ti,hwmods = "rtc";
- clocks = <&clkdiv32k_ick>;
+ clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
clock-names = "int-clk";
};
@@ -1014,4 +1022,4 @@
};
};
-/include/ "am33xx-clocks.dtsi"
+#include "am33xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index 4714a59fd86d..2f2984db1c26 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/am4.h>
/ {
compatible = "ti,am4372", "ti,am43";
@@ -163,9 +164,12 @@
};
prcm: prcm@1f0000 {
- compatible = "ti,am4-prcm";
+ compatible = "ti,am4-prcm", "simple-bus";
reg = <0x1f0000 0x11000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1f0000 0x11000>;
prcm_clocks: clocks {
#address-cells = <1>;
@@ -346,6 +350,8 @@
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-alwon;
ti,hwmods = "timer1";
+ clocks = <&timer1_fck>;
+ clock-names = "fck";
};
timer2: timer@48040000 {
@@ -353,6 +359,8 @@
reg = <0x48040000 0x400>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer2";
+ clocks = <&timer2_fck>;
+ clock-names = "fck";
};
timer3: timer@48042000 {
@@ -993,7 +1001,7 @@
reg = <0x483a8000 0x8000>;
syscon-phy-power = <&scm_conf 0x620>;
clocks = <&usb_phy0_always_on_clk32k>,
- <&usb_otg_ss0_refclk960m>;
+ <&l4_per_clkctrl AM4_USB_OTG_SS0_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
status = "disabled";
@@ -1012,7 +1020,7 @@
reg = <0x483e8000 0x8000>;
syscon-phy-power = <&scm_conf 0x628>;
clocks = <&usb_phy1_always_on_clk32k>,
- <&usb_otg_ss1_refclk960m>;
+ <&l4_per_clkctrl AM4_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
status = "disabled";
@@ -1175,4 +1183,4 @@
};
};
-/include/ "am43xx-clocks.dtsi"
+#include "am43xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/am43x-epos-evm.dts b/arch/arm/boot/dts/am43x-epos-evm.dts
index a04d79ec212a..d3363fbe4240 100644
--- a/arch/arm/boot/dts/am43x-epos-evm.dts
+++ b/arch/arm/boot/dts/am43x-epos-evm.dts
@@ -985,7 +985,7 @@
rx-num-evt = <32>;
};
-&synctimer_32kclk {
+&mux_synctimer32k_ck {
assigned-clocks = <&mux_synctimer32k_ck>;
assigned-clock-parents = <&clkdiv32k_ick>;
};
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi
index 430be5829f8f..a7037a4b4fd4 100644
--- a/arch/arm/boot/dts/am43xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am43xx-clocks.dtsi
@@ -524,54 +524,6 @@
reg = <0x4240>;
};
- gpio0_dbclk: gpio0_dbclk@2b68 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&gpio0_dbclk_mux_ck>;
- ti,bit-shift = <8>;
- reg = <0x2b68>;
- };
-
- gpio1_dbclk: gpio1_dbclk@8c78 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ick>;
- ti,bit-shift = <8>;
- reg = <0x8c78>;
- };
-
- gpio2_dbclk: gpio2_dbclk@8c80 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ick>;
- ti,bit-shift = <8>;
- reg = <0x8c80>;
- };
-
- gpio3_dbclk: gpio3_dbclk@8c88 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ick>;
- ti,bit-shift = <8>;
- reg = <0x8c88>;
- };
-
- gpio4_dbclk: gpio4_dbclk@8c90 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ick>;
- ti,bit-shift = <8>;
- reg = <0x8c90>;
- };
-
- gpio5_dbclk: gpio5_dbclk@8c98 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkdiv32k_ick>;
- ti,bit-shift = <8>;
- reg = <0x8c98>;
- };
-
mmc_clk: mmc_clk {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -629,14 +581,6 @@
reg = <0x4230>;
};
- synctimer_32kclk: synctimer_32kclk@2a30 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&mux_synctimer32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x2a30>;
- };
-
timer8_fck: timer8_fck@421c {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -763,110 +707,76 @@
ti,bit-shift = <8>;
reg = <0x2a48>;
};
+};
- usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m@8a60 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_per_clkdcoldo>;
- ti,bit-shift = <8>;
- reg = <0x8a60>;
- };
-
- usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@8a68 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_per_clkdcoldo>;
- ti,bit-shift = <8>;
- reg = <0x8a68>;
- };
-
- clkout1_osc_div_ck: clkout1_osc_div_ck {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&sys_clkin_ck>;
- ti,bit-shift = <20>;
- ti,max-div = <4>;
- reg = <0x4100>;
- };
-
- clkout1_src2_mux_ck: clkout1_src2_mux_ck {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
- <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
- <&dpll_mpu_m2_ck>;
- reg = <0x4100>;
- };
-
- clkout1_src2_pre_div_ck: clkout1_src2_pre_div_ck {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&clkout1_src2_mux_ck>;
- ti,bit-shift = <4>;
- ti,max-div = <8>;
- reg = <0x4100>;
- };
-
- clkout1_src2_post_div_ck: clkout1_src2_post_div_ck {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&clkout1_src2_pre_div_ck>;
- ti,bit-shift = <8>;
- ti,max-div = <32>;
- ti,index-power-of-two;
- reg = <0x4100>;
- };
-
- clkout1_mux_ck: clkout1_mux_ck {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
- <&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
- ti,bit-shift = <16>;
- reg = <0x4100>;
- };
-
- clkout1_ck: clkout1_ck {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkout1_mux_ck>;
- ti,bit-shift = <23>;
- reg = <0x4100>;
- };
-
- clkout2_src_mux_ck: clkout2_src_mux_ck {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
- <&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
- <&dpll_mpu_m2_ck>, <&dpll_extdev_ck>;
- reg = <0x4108>;
- };
-
- clkout2_pre_div_ck: clkout2_pre_div_ck {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&clkout2_src_mux_ck>;
- ti,bit-shift = <4>;
- ti,max-div = <8>;
- reg = <0x4108>;
- };
-
- clkout2_post_div_ck: clkout2_post_div_ck {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&clkout2_pre_div_ck>;
- ti,bit-shift = <8>;
- ti,max-div = <32>;
- ti,index-power-of-two;
- reg = <0x4108>;
- };
-
- clkout2_ck: clkout2_ck {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&clkout2_post_div_ck>;
- ti,bit-shift = <16>;
- reg = <0x4108>;
+&prcm {
+ l4_wkup_cm: l4_wkup_cm@2800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x2800 0x400>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x2800 0x400>;
+
+ l4_wkup_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x34c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ mpu_cm: mpu_cm@8300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x8300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x8300 0x100>;
+
+ mpu_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ gfx_l3_cm: gfx_l3_cm@8400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x8400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x8400 0x100>;
+
+ gfx_l3_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_rtc_cm: l4_rtc_cm@8500 {
+ compatible = "ti,omap4-cm";
+ reg = <0x8500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x8500 0x100>;
+
+ l4_rtc_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_per_cm: l4_per_cm@8800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x8800 0xc00>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x8800 0xc00>;
+
+ l4_per_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xb04>;
+ #clock-cells = <2>;
+ };
};
};
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
index 49aeecd312b4..74d1d0dab336 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
@@ -554,7 +554,7 @@
&mcasp3 {
#sound-dai-cells = <0>;
- assigned-clocks = <&mcasp3_ahclkx_mux>;
+ assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&sys_clkin2>;
status = "okay";
diff --git a/arch/arm/boot/dts/dm814x-clocks.dtsi b/arch/arm/boot/dts/dm814x-clocks.dtsi
index c4671af0a28d..f80525a290bb 100644
--- a/arch/arm/boot/dts/dm814x-clocks.dtsi
+++ b/arch/arm/boot/dts/dm814x-clocks.dtsi
@@ -337,3 +337,33 @@
clock-frequency = <20000000>;
};
};
+
+&prcm {
+ default_cm: default_cm@500 {
+ compatible = "ti,omap4-cm";
+ reg = <0x500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x500 0x100>;
+
+ default_clkctrl: clk@0 {
+ compatible = "ti,clkctrl";
+ reg = <0x0 0x5c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ alwon_cm: alwon_cm@1400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1400 0x300>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1400 0x300>;
+
+ alwon_clkctrl: clk@0 {
+ compatible = "ti,clkctrl";
+ reg = <0x0 0x228>;
+ #clock-cells = <2>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi
index 681f5487406e..601c57afd4fe 100644
--- a/arch/arm/boot/dts/dm814x.dtsi
+++ b/arch/arm/boot/dts/dm814x.dtsi
@@ -250,6 +250,8 @@
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
+ clocks = <&timer1_fck>;
+ clock-names = "fck";
};
uart1: uart@20000 {
@@ -287,6 +289,8 @@
reg = <0x40000 0x2000>;
interrupts = <68>;
ti,hwmods = "timer2";
+ clocks = <&timer2_fck>;
+ clock-names = "fck";
};
timer3: timer@42000 {
diff --git a/arch/arm/boot/dts/dm816x-clocks.dtsi b/arch/arm/boot/dts/dm816x-clocks.dtsi
index 51865eb84a80..1efd4e23e50d 100644
--- a/arch/arm/boot/dts/dm816x-clocks.dtsi
+++ b/arch/arm/boot/dts/dm816x-clocks.dtsi
@@ -248,3 +248,33 @@
reg = <0x03a8>;
};
};
+
+&prcm {
+ default_cm: default_cm@500 {
+ compatible = "ti,omap4-cm";
+ reg = <0x500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x500 0x100>;
+
+ default_clkctrl: clk@0 {
+ compatible = "ti,clkctrl";
+ reg = <0x0 0x5c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ alwon_cm: alwon_cm@1400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1400 0x300>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1400 0x300>;
+
+ alwon_clkctrl: clk@0 {
+ compatible = "ti,clkctrl";
+ reg = <0x0 0x208>;
+ #clock-cells = <2>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index 566b2a8c8b96..1edc2b48b254 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -67,8 +67,11 @@
ranges;
prcm: prcm@48180000 {
- compatible = "ti,dm816-prcm";
+ compatible = "ti,dm816-prcm", "simple-bus";
reg = <0x48180000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x48180000 0x4000>;
prcm_clocks: clocks {
#address-cells = <1>;
@@ -331,6 +334,8 @@
interrupts = <67>;
ti,hwmods = "timer1";
ti,timer-alwon;
+ clocks = <&timer1_fck>;
+ clock-names = "fck";
};
timer2: timer@48040000 {
@@ -338,6 +343,8 @@
reg = <0x48040000 0x2000>;
interrupts = <68>;
ti,hwmods = "timer2";
+ clocks = <&timer2_fck>;
+ clock-names = "fck";
};
timer3: timer@48042000 {
diff --git a/arch/arm/boot/dts/dra7-evm-common.dtsi b/arch/arm/boot/dts/dra7-evm-common.dtsi
index e088bb93636a..05a7b1a01bc3 100644
--- a/arch/arm/boot/dts/dra7-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra7-evm-common.dtsi
@@ -204,7 +204,7 @@
&atl {
assigned-clocks = <&abe_dpll_sys_clk_mux>,
- <&atl_gfclk_mux>,
+ <&atl_clkctrl DRA7_ATL_CLKCTRL 26>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
@@ -222,7 +222,7 @@
&mcasp3 {
#sound-dai-cells = <0>;
- assigned-clocks = <&mcasp3_ahclkx_mux>;
+ assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index ac9216293b7c..a1d7178a3966 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/dra.h>
+#include <dt-bindings/clock/dra7.h>
#define MAX_SOURCES 400
@@ -224,8 +225,12 @@
};
cm_core_aon: cm_core_aon@5000 {
- compatible = "ti,dra7-cm-core-aon";
+ compatible = "ti,dra7-cm-core-aon",
+ "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
reg = <0x5000 0x2000>;
+ ranges = <0 0x5000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
@@ -237,8 +242,11 @@
};
cm_core: cm_core@8000 {
- compatible = "ti,dra7-cm-core";
+ compatible = "ti,dra7-cm-core", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
reg = <0x8000 0x3000>;
+ ranges = <0 0x8000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
@@ -263,9 +271,12 @@
};
prm: prm@6000 {
- compatible = "ti,dra7-prm";
+ compatible = "ti,dra7-prm", "simple-bus";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x6000 0x3000>;
prm_clocks: clocks {
#address-cells = <1>;
@@ -876,6 +887,8 @@
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
ti,timer-alwon;
+ clock-names = "fck";
+ clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
};
timer2: timer@48032000 {
@@ -1358,7 +1371,7 @@
#address-cells = <1>;
#size-cells = <0>;
ti,hwmods = "qspi";
- clocks = <&qspi_gfclk_div>;
+ clocks = <&l4per_clkctrl DRA7_QSPI_CLKCTRL 25>;
clock-names = "fck";
num-cs = <4>;
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
@@ -1380,7 +1393,8 @@
<0x4A096800 0x40>; /* pll_ctrl */
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
syscon-phy-power = <&scm_conf 0x374>;
- clocks = <&sys_clkin1>, <&sata_ref_clk>;
+ clocks = <&sys_clkin1>,
+ <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
clock-names = "sysclk", "refclk";
syscon-pllreset = <&scm_conf 0x3fc>;
#phy-cells = <0>;
@@ -1395,9 +1409,9 @@
syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
- <&optfclk_pciephy1_32khz>,
- <&optfclk_pciephy1_clk>,
- <&optfclk_pciephy1_div_clk>,
+ <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 8>,
+ <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 9>,
+ <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 10>,
<&optfclk_pciephy_div>,
<&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2",
@@ -1415,9 +1429,9 @@
syscon-pcs = <&scm_conf_pcie 0x10>;
clocks = <&dpll_pcie_ref_ck>,
<&dpll_pcie_ref_m2ldo_ck>,
- <&optfclk_pciephy2_32khz>,
- <&optfclk_pciephy2_clk>,
- <&optfclk_pciephy2_div_clk>,
+ <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 8>,
+ <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 9>,
+ <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 10>,
<&optfclk_pciephy_div>,
<&sys_clkin1>;
clock-names = "dpll_ref", "dpll_ref_m2",
@@ -1434,7 +1448,7 @@
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
phys = <&sata_phy>;
phy-names = "sata-phy";
- clocks = <&sata_ref_clk>;
+ clocks = <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>;
ti,hwmods = "sata";
ports-implemented = <0x1>;
};
@@ -1462,7 +1476,7 @@
reg = <0x4a084000 0x400>;
syscon-phy-power = <&scm_conf 0x300>;
clocks = <&usb_phy1_always_on_clk32k>,
- <&usb_otg_ss1_refclk960m>;
+ <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk",
"refclk";
#phy-cells = <0>;
@@ -1474,7 +1488,7 @@
reg = <0x4a085000 0x400>;
syscon-phy-power = <&scm_conf 0xe74>;
clocks = <&usb_phy2_always_on_clk32k>,
- <&usb_otg_ss2_refclk960m>;
+ <&l3init_clkctrl DRA7_USB_OTG_SS2_CLKCTRL 8>;
clock-names = "wkupclk",
"refclk";
#phy-cells = <0>;
@@ -1489,7 +1503,7 @@
syscon-phy-power = <&scm_conf 0x370>;
clocks = <&usb_phy3_always_on_clk32k>,
<&sys_clkin1>,
- <&usb_otg_ss1_refclk960m>;
+ <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>;
clock-names = "wkupclk",
"sysclk",
"refclk";
@@ -1636,7 +1650,7 @@
ti,hwmods = "atl";
ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
<&atl_clkin2_ck>, <&atl_clkin3_ck>;
- clocks = <&atl_gfclk_mux>;
+ clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
clock-names = "fck";
status = "disabled";
};
@@ -1652,8 +1666,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
dma-names = "tx", "rx";
- clocks = <&mcasp1_aux_gfclk_mux>, <&mcasp1_ahclkx_mux>,
- <&mcasp1_ahclkr_mux>;
+ clocks = <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 24>,
+ <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled";
};
@@ -1669,8 +1683,9 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
dma-names = "tx", "rx";
- clocks = <&mcasp2_aux_gfclk_mux>, <&mcasp2_ahclkx_mux>,
- <&mcasp2_ahclkr_mux>;
+ clocks = <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 22>,
+ <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 24>,
+ <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled";
};
@@ -1686,7 +1701,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
dma-names = "tx", "rx";
- clocks = <&mcasp3_aux_gfclk_mux>, <&mcasp3_ahclkx_mux>;
+ clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 22>,
+ <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@@ -1702,7 +1718,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
dma-names = "tx", "rx";
- clocks = <&mcasp4_aux_gfclk_mux>, <&mcasp4_ahclkx_mux>;
+ clocks = <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 22>,
+ <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@@ -1718,7 +1735,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
dma-names = "tx", "rx";
- clocks = <&mcasp5_aux_gfclk_mux>, <&mcasp5_ahclkx_mux>;
+ clocks = <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 22>,
+ <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@@ -1734,7 +1752,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
dma-names = "tx", "rx";
- clocks = <&mcasp6_aux_gfclk_mux>, <&mcasp6_ahclkx_mux>;
+ clocks = <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 22>,
+ <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@@ -1750,7 +1769,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
dma-names = "tx", "rx";
- clocks = <&mcasp7_aux_gfclk_mux>, <&mcasp7_ahclkx_mux>;
+ clocks = <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 22>,
+ <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@@ -1766,7 +1786,8 @@
interrupt-names = "tx", "rx";
dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
dma-names = "tx", "rx";
- clocks = <&mcasp8_aux_gfclk_mux>, <&mcasp8_ahclkx_mux>;
+ clocks = <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 22>,
+ <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 24>;
clock-names = "fck", "ahclkx";
status = "disabled";
};
@@ -1788,7 +1809,7 @@
mac: ethernet@48484000 {
compatible = "ti,dra7-cpsw","ti,cpsw";
ti,hwmods = "gmac";
- clocks = <&gmac_main_clk>, <&gmac_rft_clk_mux>;
+ clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>;
clock-names = "fck", "cpts";
cpdma_channels = <8>;
ale_entries = <1024>;
@@ -1858,7 +1879,7 @@
reg = <0x4ae3c000 0x2000>;
syscon-raminit = <&scm_conf 0x558 0>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dcan1_sys_clk_mux>;
+ clocks = <&wkupaon_clkctrl DRA7_DCAN1_CLKCTRL 24>;
status = "disabled";
};
@@ -1889,7 +1910,7 @@
reg = <0x58001000 0x1000>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
- clocks = <&dss_dss_clk>;
+ clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
/* CTRL_CORE_SMA_SW_1 */
syscon-pol = <&scm_conf 0x534>;
@@ -1905,7 +1926,8 @@
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_hdmi";
- clocks = <&dss_48mhz_clk>, <&dss_hdmi_clk>;
+ clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
+ <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
};
@@ -2089,4 +2111,4 @@
temperature = <120000>; /* milli Celsius */
};
-/include/ "dra7xx-clocks.dtsi"
+#include "dra7xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index 2e485a13dfd7..e85f560a2f78 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -514,7 +514,7 @@
&atl {
assigned-clocks = <&abe_dpll_sys_clk_mux>,
- <&atl_gfclk_mux>,
+ <&atl_clkctrl DRA7_ATL_CLKCTRL 26>,
<&dpll_abe_ck>,
<&dpll_abe_m2x2_ck>,
<&atl_clkin2_ck>;
@@ -532,7 +532,7 @@
&mcasp3 {
#sound-dai-cells = <0>;
- assigned-clocks = <&mcasp3_ahclkx_mux>;
+ assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
assigned-clock-parents = <&atl_clkin2_ck>;
status = "okay";
diff --git a/arch/arm/boot/dts/dra72x.dtsi b/arch/arm/boot/dts/dra72x.dtsi
index 67107605fb4c..a06d39919bf4 100644
--- a/arch/arm/boot/dts/dra72x.dtsi
+++ b/arch/arm/boot/dts/dra72x.dtsi
@@ -25,8 +25,8 @@
<0x58004300 0x20>;
reg-names = "dss", "pll1_clkctrl", "pll1";
- clocks = <&dss_dss_clk>,
- <&dss_video1_clk>;
+ clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>,
+ <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>;
clock-names = "fck", "video1_clk";
};
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 24e6746c5b26..24ff17bae4c6 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -93,9 +93,9 @@
reg-names = "dss", "pll1_clkctrl", "pll1",
"pll2_clkctrl", "pll2";
- clocks = <&dss_dss_clk>,
- <&dss_video1_clk>,
- <&dss_video2_clk>;
+ clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>,
+ <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 12>,
+ <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 13>;
clock-names = "fck", "video1_clk", "video2_clk";
};
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index e62b62875cba..69562cdbeada 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -11,25 +11,25 @@
atl_clkin0_ck: atl_clkin0_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
- clocks = <&atl_gfclk_mux>;
+ clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
};
atl_clkin1_ck: atl_clkin1_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
- clocks = <&atl_gfclk_mux>;
+ clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
};
atl_clkin2_ck: atl_clkin2_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
- clocks = <&atl_gfclk_mux>;
+ clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
};
atl_clkin3_ck: atl_clkin3_ck {
#clock-cells = <0>;
compatible = "ti,dra7-atl-clock";
- clocks = <&atl_gfclk_mux>;
+ clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
};
hdmi_clkin_ck: hdmi_clkin_ck {
@@ -809,70 +809,6 @@
assigned-clock-parents = <&dpll_core_h22x2_ck>;
};
- mcasp1_ahclkr_mux: mcasp1_ahclkr_mux@550 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <28>;
- reg = <0x0550>;
- };
-
- mcasp1_ahclkx_mux: mcasp1_ahclkx_mux@550 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <24>;
- reg = <0x0550>;
- };
-
- mcasp1_aux_gfclk_mux: mcasp1_aux_gfclk_mux@550 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
- ti,bit-shift = <22>;
- reg = <0x0550>;
- };
-
- timer5_gfclk_mux: timer5_gfclk_mux@558 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
- ti,bit-shift = <24>;
- reg = <0x0558>;
- };
-
- timer6_gfclk_mux: timer6_gfclk_mux@560 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
- ti,bit-shift = <24>;
- reg = <0x0560>;
- };
-
- timer7_gfclk_mux: timer7_gfclk_mux@568 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
- ti,bit-shift = <24>;
- reg = <0x0568>;
- };
-
- timer8_gfclk_mux: timer8_gfclk_mux@570 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>, <&clkoutmux0_clk_mux>;
- ti,bit-shift = <24>;
- reg = <0x0570>;
- };
-
- uart6_gfclk_mux: uart6_gfclk_mux@580 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x0580>;
- };
-
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -1188,39 +1124,8 @@
clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
reg = <0x0108>;
};
-
- gpio1_dbclk: gpio1_dbclk@1838 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1838>;
- };
-
- dcan1_sys_clk_mux: dcan1_sys_clk_mux@1888 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin1>, <&sys_clkin2>;
- ti,bit-shift = <24>;
- reg = <0x1888>;
- };
-
- timer1_gfclk_mux: timer1_gfclk_mux@1840 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x1840>;
- };
-
- uart10_gfclk_mux: uart10_gfclk_mux@1880 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1880>;
- };
};
+
&cm_core_clocks {
dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
#clock-cells = <0>;
@@ -1255,22 +1160,6 @@
reg = <0x021c>, <0x0220>;
};
- optfclk_pciephy1_32khz: optfclk_pciephy1_32khz@4a0093b0 {
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- #clock-cells = <0>;
- reg = <0x13b0>;
- ti,bit-shift = <8>;
- };
-
- optfclk_pciephy2_32khz: optfclk_pciephy2_32khz@4a0093b8 {
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- #clock-cells = <0>;
- reg = <0x13b8>;
- ti,bit-shift = <8>;
- };
-
optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
compatible = "ti,divider-clock";
clocks = <&apll_pcie_ck>;
@@ -1281,38 +1170,6 @@
ti,max-div = <2>;
};
- optfclk_pciephy1_clk: optfclk_pciephy1_clk@4a0093b0 {
- compatible = "ti,gate-clock";
- clocks = <&apll_pcie_ck>;
- #clock-cells = <0>;
- reg = <0x13b0>;
- ti,bit-shift = <9>;
- };
-
- optfclk_pciephy2_clk: optfclk_pciephy2_clk@4a0093b8 {
- compatible = "ti,gate-clock";
- clocks = <&apll_pcie_ck>;
- #clock-cells = <0>;
- reg = <0x13b8>;
- ti,bit-shift = <9>;
- };
-
- optfclk_pciephy1_div_clk: optfclk_pciephy1_div_clk@4a0093b0 {
- compatible = "ti,gate-clock";
- clocks = <&optfclk_pciephy_div>;
- #clock-cells = <0>;
- reg = <0x13b0>;
- ti,bit-shift = <10>;
- };
-
- optfclk_pciephy2_div_clk: optfclk_pciephy2_div_clk@4a0093b8 {
- compatible = "ti,gate-clock";
- clocks = <&optfclk_pciephy_div>;
- #clock-cells = <0>;
- reg = <0x13b8>;
- ti,bit-shift = <10>;
- };
-
apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
#clock-cells = <0>;
compatible = "fixed-factor-clock";
@@ -1541,167 +1398,6 @@
reg = <0x06c0>;
};
- dss_32khz_clk: dss_32khz_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <11>;
- reg = <0x1120>;
- };
-
- dss_48mhz_clk: dss_48mhz_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_48m_fclk>;
- ti,bit-shift = <9>;
- reg = <0x1120>;
- };
-
- dss_dss_clk: dss_dss_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_per_h12x2_ck>;
- ti,bit-shift = <8>;
- reg = <0x1120>;
- ti,set-rate-parent;
- };
-
- dss_hdmi_clk: dss_hdmi_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&hdmi_dpll_clk_mux>;
- ti,bit-shift = <10>;
- reg = <0x1120>;
- };
-
- dss_video1_clk: dss_video1_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&video1_dpll_clk_mux>;
- ti,bit-shift = <12>;
- reg = <0x1120>;
- };
-
- dss_video2_clk: dss_video2_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&video2_dpll_clk_mux>;
- ti,bit-shift = <13>;
- reg = <0x1120>;
- };
-
- gpio2_dbclk: gpio2_dbclk@1760 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1760>;
- };
-
- gpio3_dbclk: gpio3_dbclk@1768 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1768>;
- };
-
- gpio4_dbclk: gpio4_dbclk@1770 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1770>;
- };
-
- gpio5_dbclk: gpio5_dbclk@1778 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1778>;
- };
-
- gpio6_dbclk: gpio6_dbclk@1780 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1780>;
- };
-
- gpio7_dbclk: gpio7_dbclk@1810 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1810>;
- };
-
- gpio8_dbclk: gpio8_dbclk@1818 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1818>;
- };
-
- mmc1_clk32k: mmc1_clk32k@1328 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1328>;
- };
-
- mmc2_clk32k: mmc2_clk32k@1330 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1330>;
- };
-
- mmc3_clk32k: mmc3_clk32k@1820 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1820>;
- };
-
- mmc4_clk32k: mmc4_clk32k@1828 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1828>;
- };
-
- sata_ref_clk: sata_ref_clk@1388 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_clkin1>;
- ti,bit-shift = <8>;
- reg = <0x1388>;
- };
-
- usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m@13f0 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_960m_gfclk>;
- ti,bit-shift = <8>;
- reg = <0x13f0>;
- };
-
- usb_otg_ss2_refclk960m: usb_otg_ss2_refclk960m@1340 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_960m_gfclk>;
- ti,bit-shift = <8>;
- reg = <0x1340>;
- };
-
usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1726,38 +1422,6 @@
reg = <0x0698>;
};
- atl_dpll_clk_mux: atl_dpll_clk_mux@c00 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_32k_ck>, <&video1_clkin_ck>, <&video2_clkin_ck>, <&hdmi_clkin_ck>;
- ti,bit-shift = <24>;
- reg = <0x0c00>;
- };
-
- atl_gfclk_mux: atl_gfclk_mux@c00 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&l3_iclk_div>, <&dpll_abe_m2_ck>, <&atl_dpll_clk_mux>;
- ti,bit-shift = <26>;
- reg = <0x0c00>;
- };
-
- rmii_50mhz_clk_mux: rmii_50mhz_clk_mux@13d0 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
- ti,bit-shift = <24>;
- reg = <0x13d0>;
- };
-
- gmac_rft_clk_mux: gmac_rft_clk_mux@13d0 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&video1_clkin_ck>, <&video2_clkin_ck>, <&dpll_abe_m2_ck>, <&hdmi_clkin_ck>, <&l3_iclk_div>;
- ti,bit-shift = <25>;
- reg = <0x13d0>;
- };
-
gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -1787,362 +1451,6 @@
ti,dividers = <8>, <16>, <32>;
};
- mcasp2_ahclkr_mux: mcasp2_ahclkr_mux@1860 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <28>;
- reg = <0x1860>;
- };
-
- mcasp2_ahclkx_mux: mcasp2_ahclkx_mux@1860 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <24>;
- reg = <0x1860>;
- };
-
- mcasp2_aux_gfclk_mux: mcasp2_aux_gfclk_mux@1860 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
- ti,bit-shift = <22>;
- reg = <0x1860>;
- };
-
- mcasp3_ahclkx_mux: mcasp3_ahclkx_mux@1868 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <24>;
- reg = <0x1868>;
- assigned-clocks = <&mcasp3_ahclkx_mux>;
- assigned-clock-parents = <&abe_24m_fclk>;
- };
-
- mcasp3_aux_gfclk_mux: mcasp3_aux_gfclk_mux@1868 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
- ti,bit-shift = <22>;
- reg = <0x1868>;
- };
-
- mcasp4_ahclkx_mux: mcasp4_ahclkx_mux@1898 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <24>;
- reg = <0x1898>;
- };
-
- mcasp4_aux_gfclk_mux: mcasp4_aux_gfclk_mux@1898 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
- ti,bit-shift = <22>;
- reg = <0x1898>;
- };
-
- mcasp5_ahclkx_mux: mcasp5_ahclkx_mux@1878 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <24>;
- reg = <0x1878>;
- };
-
- mcasp5_aux_gfclk_mux: mcasp5_aux_gfclk_mux@1878 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
- ti,bit-shift = <22>;
- reg = <0x1878>;
- };
-
- mcasp6_ahclkx_mux: mcasp6_ahclkx_mux@1904 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <24>;
- reg = <0x1904>;
- };
-
- mcasp6_aux_gfclk_mux: mcasp6_aux_gfclk_mux@1904 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
- ti,bit-shift = <22>;
- reg = <0x1904>;
- };
-
- mcasp7_ahclkx_mux: mcasp7_ahclkx_mux@1908 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <24>;
- reg = <0x1908>;
- };
-
- mcasp7_aux_gfclk_mux: mcasp7_aux_gfclk_mux@1908 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
- ti,bit-shift = <22>;
- reg = <0x1908>;
- };
-
- mcasp8_ahclkx_mux: mcasp8_ahclkx_mux@1890 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&abe_sys_clk_div>, <&func_24m_clk>, <&atl_clkin3_ck>, <&atl_clkin2_ck>, <&atl_clkin1_ck>, <&atl_clkin0_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&mlb_clk>, <&mlbp_clk>;
- ti,bit-shift = <22>;
- reg = <0x1890>;
- };
-
- mcasp8_aux_gfclk_mux: mcasp8_aux_gfclk_mux@1890 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&per_abe_x1_gfclk2_div>, <&video1_clk2_div>, <&video2_clk2_div>, <&hdmi_clk2_div>;
- ti,bit-shift = <24>;
- reg = <0x1890>;
- };
-
- mmc1_fclk_mux: mmc1_fclk_mux@1328 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1328>;
- };
-
- mmc1_fclk_div: mmc1_fclk_div@1328 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&mmc1_fclk_mux>;
- ti,bit-shift = <25>;
- ti,max-div = <4>;
- reg = <0x1328>;
- ti,index-power-of-two;
- };
-
- mmc2_fclk_mux: mmc2_fclk_mux@1330 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1330>;
- };
-
- mmc2_fclk_div: mmc2_fclk_div@1330 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&mmc2_fclk_mux>;
- ti,bit-shift = <25>;
- ti,max-div = <4>;
- reg = <0x1330>;
- ti,index-power-of-two;
- };
-
- mmc3_gfclk_mux: mmc3_gfclk_mux@1820 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1820>;
- };
-
- mmc3_gfclk_div: mmc3_gfclk_div@1820 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&mmc3_gfclk_mux>;
- ti,bit-shift = <25>;
- ti,max-div = <4>;
- reg = <0x1820>;
- ti,index-power-of-two;
- };
-
- mmc4_gfclk_mux: mmc4_gfclk_mux@1828 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1828>;
- };
-
- mmc4_gfclk_div: mmc4_gfclk_div@1828 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&mmc4_gfclk_mux>;
- ti,bit-shift = <25>;
- ti,max-div = <4>;
- reg = <0x1828>;
- ti,index-power-of-two;
- };
-
- qspi_gfclk_mux: qspi_gfclk_mux@1838 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_128m_clk>, <&dpll_per_h13x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1838>;
- };
-
- qspi_gfclk_div: qspi_gfclk_div@1838 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&qspi_gfclk_mux>;
- ti,bit-shift = <25>;
- ti,max-div = <4>;
- reg = <0x1838>;
- ti,index-power-of-two;
- };
-
- timer10_gfclk_mux: timer10_gfclk_mux@1728 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x1728>;
- };
-
- timer11_gfclk_mux: timer11_gfclk_mux@1730 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x1730>;
- };
-
- timer13_gfclk_mux: timer13_gfclk_mux@17c8 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x17c8>;
- };
-
- timer14_gfclk_mux: timer14_gfclk_mux@17d0 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x17d0>;
- };
-
- timer15_gfclk_mux: timer15_gfclk_mux@17d8 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x17d8>;
- };
-
- timer16_gfclk_mux: timer16_gfclk_mux@1830 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x1830>;
- };
-
- timer2_gfclk_mux: timer2_gfclk_mux@1738 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x1738>;
- };
-
- timer3_gfclk_mux: timer3_gfclk_mux@1740 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x1740>;
- };
-
- timer4_gfclk_mux: timer4_gfclk_mux@1748 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x1748>;
- };
-
- timer9_gfclk_mux: timer9_gfclk_mux@1750 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&timer_sys_clk_div>, <&sys_32k_ck>, <&sys_clkin2>, <&ref_clkin0_ck>, <&ref_clkin1_ck>, <&ref_clkin2_ck>, <&ref_clkin3_ck>, <&abe_giclk_div>, <&video1_div_clk>, <&video2_div_clk>, <&hdmi_div_clk>;
- ti,bit-shift = <24>;
- reg = <0x1750>;
- };
-
- uart1_gfclk_mux: uart1_gfclk_mux@1840 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1840>;
- };
-
- uart2_gfclk_mux: uart2_gfclk_mux@1848 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1848>;
- };
-
- uart3_gfclk_mux: uart3_gfclk_mux@1850 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1850>;
- };
-
- uart4_gfclk_mux: uart4_gfclk_mux@1858 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1858>;
- };
-
- uart5_gfclk_mux: uart5_gfclk_mux@1870 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1870>;
- };
-
- uart7_gfclk_mux: uart7_gfclk_mux@18d0 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x18d0>;
- };
-
- uart8_gfclk_mux: uart8_gfclk_mux@18e0 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x18e0>;
- };
-
- uart9_gfclk_mux: uart9_gfclk_mux@18e8 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_48m_fclk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x18e8>;
- };
-
vip1_gclk_mux: vip1_gclk_mux@1020 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -2216,3 +1524,210 @@
reg = <0x6c4>;
};
};
+
+&cm_core_aon {
+ mpu_cm: mpu_cm@300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x300 0x100>;
+
+ mpu_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ ipu_cm: ipu_cm@500 {
+ compatible = "ti,omap4-cm";
+ reg = <0x500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x500 0x100>;
+
+ ipu_clkctrl: clk@40 {
+ compatible = "ti,clkctrl";
+ reg = <0x40 0x44>;
+ #clock-cells = <2>;
+ };
+ };
+
+ rtc_cm: rtc_cm@700 {
+ compatible = "ti,omap4-cm";
+ reg = <0x700 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x700 0x100>;
+
+ rtc_clkctrl: clk@40 {
+ compatible = "ti,clkctrl";
+ reg = <0x40 0x8>;
+ #clock-cells = <2>;
+ };
+ };
+
+};
+
+&cm_core {
+ coreaon_cm: coreaon_cm@600 {
+ compatible = "ti,omap4-cm";
+ reg = <0x600 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x600 0x100>;
+
+ coreaon_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x1c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3main1_cm: l3main1_cm@700 {
+ compatible = "ti,omap4-cm";
+ reg = <0x700 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x700 0x100>;
+
+ l3main1_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x74>;
+ #clock-cells = <2>;
+ };
+ };
+
+ dma_cm: dma_cm@a00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xa00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa00 0x100>;
+
+ dma_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ emif_cm: emif_cm@b00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xb00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xb00 0x100>;
+
+ emif_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ atl_cm: atl_cm@c00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xc00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xc00 0x100>;
+
+ atl_clkctrl: clk@0 {
+ compatible = "ti,clkctrl";
+ reg = <0x0 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4cfg_cm: l4cfg_cm@d00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xd00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xd00 0x100>;
+
+ l4cfg_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x84>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3instr_cm: l3instr_cm@e00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xe00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xe00 0x100>;
+
+ l3instr_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc>;
+ #clock-cells = <2>;
+ };
+ };
+
+ dss_cm: dss_cm@1100 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1100 0x100>;
+
+ dss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x14>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3init_cm: l3init_cm@1300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1300 0x100>;
+
+ l3init_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xd4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4per_cm: l4per_cm@1700 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1700 0x300>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1700 0x300>;
+
+ l4per_clkctrl: clk@0 {
+ compatible = "ti,clkctrl";
+ reg = <0x0 0x20c>;
+ #clock-cells = <2>;
+
+ assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
+ assigned-clock-parents = <&abe_24m_fclk>;
+ };
+ };
+
+};
+
+&prm {
+ wkupaon_cm: wkupaon_cm@1800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1800 0x100>;
+
+ wkupaon_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x6c>;
+ #clock-cells = <2>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index cc1a07a3620f..18a11f689a1d 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>
+#include <dt-bindings/clock/omap4.h>
/ {
compatible = "ti,omap4430", "ti,omap4";
@@ -143,8 +144,11 @@
ranges = <0 0x4a000000 0x1000000>;
cm1: cm1@4000 {
- compatible = "ti,omap4-cm1";
+ compatible = "ti,omap4-cm1", "simple-bus";
reg = <0x4000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4000 0x2000>;
cm1_clocks: clocks {
#address-cells = <1>;
@@ -156,8 +160,11 @@
};
cm2: cm2@8000 {
- compatible = "ti,omap4-cm2";
+ compatible = "ti,omap4-cm2", "simple-bus";
reg = <0x8000 0x3000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x8000 0x3000>;
cm2_clocks: clocks {
#address-cells = <1>;
@@ -243,6 +250,9 @@
compatible = "ti,omap4-prm";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x6000 0x3000>;
prm_clocks: clocks {
#address-cells = <1>;
@@ -674,7 +684,7 @@
reg-names = "sys", "gdd";
ti,hwmods = "hsi";
- clocks = <&hsi_fck>;
+ clocks = <&l3_init_clkctrl OMAP4_HSI_CLKCTRL 0>;
clock-names = "hsi_fck";
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
@@ -973,6 +983,8 @@
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
ti,timer-alwon;
+ clocks = <&l4_wkup_clkctrl OMAP4_TIMER1_CLKCTRL 24>;
+ clock-names = "fck";
};
timer2: timer@48032000 {
@@ -1202,7 +1214,7 @@
reg = <0x58000000 0x80>;
status = "disabled";
ti,hwmods = "dss_core";
- clocks = <&dss_dss_clk>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
@@ -1213,7 +1225,7 @@
reg = <0x58001000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
- clocks = <&dss_dss_clk>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
};
@@ -1222,7 +1234,7 @@
reg = <0x58002000 0x1000>;
status = "disabled";
ti,hwmods = "dss_rfbi";
- clocks = <&dss_dss_clk>, <&l3_div_ck>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
clock-names = "fck", "ick";
};
@@ -1231,7 +1243,7 @@
reg = <0x58003000 0x1000>;
status = "disabled";
ti,hwmods = "dss_venc";
- clocks = <&dss_tv_clk>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
clock-names = "fck";
};
@@ -1244,7 +1256,8 @@
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_dsi1";
- clocks = <&dss_dss_clk>, <&dss_sys_clk>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
@@ -1257,7 +1270,8 @@
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_dsi2";
- clocks = <&dss_dss_clk>, <&dss_sys_clk>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
@@ -1271,7 +1285,8 @@
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_hdmi";
- clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
+ clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
+ <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
dmas = <&sdma 76>;
dma-names = "audio_tx";
@@ -1280,4 +1295,4 @@
};
};
-/include/ "omap44xx-clocks.dtsi"
+#include "omap44xx-clocks.dtsi"
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index 05732ed4f50f..279ff2f419df 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -174,14 +174,6 @@
ti,index-power-of-two;
};
- aess_fclk: aess_fclk@528 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&abe_clk>;
- ti,bit-shift = <24>;
- ti,max-div = <2>;
- reg = <0x0528>;
- };
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
#clock-cells = <0>;
@@ -464,7 +456,7 @@
ocp_abe_iclk: ocp_abe_iclk@528 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
- clocks = <&aess_fclk>;
+ clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>;
ti,bit-shift = <24>;
reg = <0x0528>;
ti,dividers = <2>, <1>;
@@ -478,156 +470,13 @@
clock-div = <4>;
};
- dmic_sync_mux_ck: dmic_sync_mux_ck@538 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
- ti,bit-shift = <25>;
- reg = <0x0538>;
- };
-
- func_dmic_abe_gfclk: func_dmic_abe_gfclk@538 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0538>;
- };
-
- mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
- ti,bit-shift = <25>;
- reg = <0x0540>;
- };
-
- func_mcasp_abe_gfclk: func_mcasp_abe_gfclk@540 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0540>;
- };
-
- mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
- ti,bit-shift = <25>;
- reg = <0x0548>;
- };
-
- func_mcbsp1_gfclk: func_mcbsp1_gfclk@548 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0548>;
- };
-
- mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
- ti,bit-shift = <25>;
- reg = <0x0550>;
- };
-
- func_mcbsp2_gfclk: func_mcbsp2_gfclk@550 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0550>;
- };
-
- mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&syc_clk_div_ck>, <&func_24m_clk>;
- ti,bit-shift = <25>;
- reg = <0x0558>;
- };
-
- func_mcbsp3_gfclk: func_mcbsp3_gfclk@558 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0558>;
- };
-
- slimbus1_fclk_1: slimbus1_fclk_1@560 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_24m_clk>;
- ti,bit-shift = <9>;
- reg = <0x0560>;
- };
-
- slimbus1_fclk_0: slimbus1_fclk_0@560 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&abe_24m_fclk>;
- ti,bit-shift = <8>;
- reg = <0x0560>;
- };
-
- slimbus1_fclk_2: slimbus1_fclk_2@560 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&pad_clks_ck>;
- ti,bit-shift = <10>;
- reg = <0x0560>;
- };
-
- slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&slimbus_clk>;
- ti,bit-shift = <11>;
- reg = <0x0560>;
- };
-
- timer5_sync_mux: timer5_sync_mux@568 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0568>;
- };
-
- timer6_sync_mux: timer6_sync_mux@570 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0570>;
- };
-
- timer7_sync_mux: timer7_sync_mux@578 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0578>;
- };
-
- timer8_sync_mux: timer8_sync_mux@580 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0580>;
- };
-
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <0>;
};
};
+
&prm_clocks {
sys_clkin_ck: sys_clkin_ck@110 {
#clock-cells = <0>;
@@ -675,22 +524,6 @@
ti,max-div = <2>;
};
- gpio1_dbclk: gpio1_dbclk@1838 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1838>;
- };
-
- dmt1_clk_mux: dmt1_clk_mux@1840 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1840>;
- };
-
usim_ck: usim_ck@1858 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
@@ -708,45 +541,10 @@
reg = <0x1858>;
};
- pmd_stm_clock_mux_ck: pmd_stm_clock_mux_ck@1a20 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
- ti,bit-shift = <20>;
- reg = <0x1a20>;
- };
-
- pmd_trace_clk_mux_ck: pmd_trace_clk_mux_ck@1a20 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&dpll_core_m6x2_ck>, <&tie_low_clock_ck>;
- ti,bit-shift = <22>;
- reg = <0x1a20>;
- };
-
- stm_clk_div_ck: stm_clk_div_ck@1a20 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&pmd_stm_clock_mux_ck>;
- ti,bit-shift = <27>;
- ti,max-div = <64>;
- reg = <0x1a20>;
- ti,index-power-of-two;
- };
-
- trace_clk_div_div_ck: trace_clk_div_div_ck@1a20 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&pmd_trace_clk_mux_ck>;
- ti,bit-shift = <24>;
- reg = <0x1a20>;
- ti,dividers = <0>, <1>, <2>, <0>, <4>;
- };
-
trace_clk_div_ck: trace_clk_div_ck {
#clock-cells = <0>;
compatible = "ti,clkdm-gate-clock";
- clocks = <&trace_clk_div_div_ck>;
+ clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>;
};
};
@@ -975,155 +773,6 @@
ti,max-div = <2>;
};
- dss_sys_clk: dss_sys_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&syc_clk_div_ck>;
- ti,bit-shift = <10>;
- reg = <0x1120>;
- };
-
- dss_tv_clk: dss_tv_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&extalt_clkin_ck>;
- ti,bit-shift = <11>;
- reg = <0x1120>;
- };
-
- dss_dss_clk: dss_dss_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_per_m5x2_ck>;
- ti,bit-shift = <8>;
- reg = <0x1120>;
- ti,set-rate-parent;
- };
-
- dss_48mhz_clk: dss_48mhz_clk@1120 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_48mc_fclk>;
- ti,bit-shift = <9>;
- reg = <0x1120>;
- };
-
- fdif_fck: fdif_fck@1028 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_m4x2_ck>;
- ti,bit-shift = <24>;
- ti,max-div = <4>;
- reg = <0x1028>;
- ti,index-power-of-two;
- };
-
- gpio2_dbclk: gpio2_dbclk@1460 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1460>;
- };
-
- gpio3_dbclk: gpio3_dbclk@1468 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1468>;
- };
-
- gpio4_dbclk: gpio4_dbclk@1470 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1470>;
- };
-
- gpio5_dbclk: gpio5_dbclk@1478 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1478>;
- };
-
- gpio6_dbclk: gpio6_dbclk@1480 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1480>;
- };
-
- sgx_clk_mux: sgx_clk_mux@1220 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dpll_core_m7x2_ck>, <&dpll_per_m7x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1220>;
- };
-
- hsi_fck: hsi_fck@1338 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- ti,max-div = <4>;
- reg = <0x1338>;
- ti,index-power-of-two;
- };
-
- iss_ctrlclk: iss_ctrlclk@1020 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_96m_fclk>;
- ti,bit-shift = <8>;
- reg = <0x1020>;
- };
-
- mcbsp4_sync_mux_ck: mcbsp4_sync_mux_ck@14e0 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_96m_fclk>, <&per_abe_nc_fclk>;
- ti,bit-shift = <25>;
- reg = <0x14e0>;
- };
-
- per_mcbsp4_gfclk: per_mcbsp4_gfclk@14e0 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcbsp4_sync_mux_ck>, <&pad_clks_ck>;
- ti,bit-shift = <24>;
- reg = <0x14e0>;
- };
-
- hsmmc1_fclk: hsmmc1_fclk@1328 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_64m_fclk>, <&func_96m_fclk>;
- ti,bit-shift = <24>;
- reg = <0x1328>;
- };
-
- hsmmc2_fclk: hsmmc2_fclk@1330 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_64m_fclk>, <&func_96m_fclk>;
- ti,bit-shift = <24>;
- reg = <0x1330>;
- };
-
- ocp2scp_usb_phy_phy_48m: ocp2scp_usb_phy_phy_48m@13e0 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_48m_fclk>;
- ti,bit-shift = <8>;
- reg = <0x13e0>;
- };
-
sha2md5_fck: sha2md5_fck@15c8 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1132,222 +781,6 @@
reg = <0x15c8>;
};
- slimbus2_fclk_1: slimbus2_fclk_1@1538 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&per_abe_24m_fclk>;
- ti,bit-shift = <9>;
- reg = <0x1538>;
- };
-
- slimbus2_fclk_0: slimbus2_fclk_0@1538 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_24mc_fclk>;
- ti,bit-shift = <8>;
- reg = <0x1538>;
- };
-
- slimbus2_slimbus_clk: slimbus2_slimbus_clk@1538 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&pad_slimbus_core_clks_ck>;
- ti,bit-shift = <10>;
- reg = <0x1538>;
- };
-
- smartreflex_core_fck: smartreflex_core_fck@638 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_wkup_clk_mux_ck>;
- ti,bit-shift = <1>;
- reg = <0x0638>;
- };
-
- smartreflex_iva_fck: smartreflex_iva_fck@630 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_wkup_clk_mux_ck>;
- ti,bit-shift = <1>;
- reg = <0x0630>;
- };
-
- smartreflex_mpu_fck: smartreflex_mpu_fck@628 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_wkup_clk_mux_ck>;
- ti,bit-shift = <1>;
- reg = <0x0628>;
- };
-
- cm2_dm10_mux: cm2_dm10_mux@1428 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1428>;
- };
-
- cm2_dm11_mux: cm2_dm11_mux@1430 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1430>;
- };
-
- cm2_dm2_mux: cm2_dm2_mux@1438 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1438>;
- };
-
- cm2_dm3_mux: cm2_dm3_mux@1440 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1440>;
- };
-
- cm2_dm4_mux: cm2_dm4_mux@1448 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1448>;
- };
-
- cm2_dm9_mux: cm2_dm9_mux@1450 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1450>;
- };
-
- usb_host_fs_fck: usb_host_fs_fck@13d0 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_48mc_fclk>;
- ti,bit-shift = <1>;
- reg = <0x13d0>;
- };
-
- utmi_p1_gfclk: utmi_p1_gfclk@1358 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&init_60m_fclk>, <&xclk60mhsp1_ck>;
- ti,bit-shift = <24>;
- reg = <0x1358>;
- };
-
- usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&utmi_p1_gfclk>;
- ti,bit-shift = <8>;
- reg = <0x1358>;
- };
-
- utmi_p2_gfclk: utmi_p2_gfclk@1358 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&init_60m_fclk>, <&xclk60mhsp2_ck>;
- ti,bit-shift = <25>;
- reg = <0x1358>;
- };
-
- usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&utmi_p2_gfclk>;
- ti,bit-shift = <9>;
- reg = <0x1358>;
- };
-
- usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&init_60m_fclk>;
- ti,bit-shift = <10>;
- reg = <0x1358>;
- };
-
- usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_usb_m2_ck>;
- ti,bit-shift = <13>;
- reg = <0x1358>;
- };
-
- usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&init_60m_fclk>;
- ti,bit-shift = <11>;
- reg = <0x1358>;
- };
-
- usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&init_60m_fclk>;
- ti,bit-shift = <12>;
- reg = <0x1358>;
- };
-
- usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_usb_m2_ck>;
- ti,bit-shift = <14>;
- reg = <0x1358>;
- };
-
- usb_host_hs_func48mclk: usb_host_hs_func48mclk@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_48mc_fclk>;
- ti,bit-shift = <15>;
- reg = <0x1358>;
- };
-
- usb_host_hs_fck: usb_host_hs_fck@1358 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&init_60m_fclk>;
- ti,bit-shift = <1>;
- reg = <0x1358>;
- };
-
- otg_60m_gfclk: otg_60m_gfclk@1360 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&utmi_phy_clkout_ck>, <&xclk60motg_ck>;
- ti,bit-shift = <24>;
- reg = <0x1360>;
- };
-
- usb_otg_hs_xclk: usb_otg_hs_xclk@1360 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&otg_60m_gfclk>;
- ti,bit-shift = <8>;
- reg = <0x1360>;
- };
-
- usb_otg_hs_ick: usb_otg_hs_ick@1360 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3_div_ck>;
- ti,bit-shift = <0>;
- reg = <0x1360>;
- };
-
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1355,44 +788,12 @@
ti,bit-shift = <8>;
reg = <0x0640>;
};
-
- usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1368 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&init_60m_fclk>;
- ti,bit-shift = <10>;
- reg = <0x1368>;
- };
-
- usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1368 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&init_60m_fclk>;
- ti,bit-shift = <8>;
- reg = <0x1368>;
- };
-
- usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1368 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&init_60m_fclk>;
- ti,bit-shift = <9>;
- reg = <0x1368>;
- };
-
- usb_tll_hs_ick: usb_tll_hs_ick@1368 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l4_div_ck>;
- ti,bit-shift = <0>;
- reg = <0x1368>;
- };
};
&cm2_clockdomains {
l3_init_clkdm: l3_init_clkdm {
compatible = "ti,clockdomain";
- clocks = <&dpll_usb_ck>, <&usb_host_fs_fck>;
+ clocks = <&dpll_usb_ck>;
};
};
@@ -1631,3 +1032,291 @@
reg = <0x0224>;
};
};
+
+&cm1 {
+ mpuss_cm: mpuss_cm@300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x300 0x100>;
+
+ mpuss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ tesla_cm: tesla_cm@400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x400 0x100>;
+
+ tesla_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ abe_cm: abe_cm@500 {
+ compatible = "ti,omap4-cm";
+ reg = <0x500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x500 0x100>;
+
+ abe_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x6c>;
+ #clock-cells = <2>;
+ };
+ };
+
+};
+
+&cm2 {
+ l4_ao_cm: l4_ao_cm@600 {
+ compatible = "ti,omap4-cm";
+ reg = <0x600 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x600 0x100>;
+
+ l4_ao_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x1c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_1_cm: l3_1_cm@700 {
+ compatible = "ti,omap4-cm";
+ reg = <0x700 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x700 0x100>;
+
+ l3_1_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_2_cm: l3_2_cm@800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x800 0x100>;
+
+ l3_2_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x14>;
+ #clock-cells = <2>;
+ };
+ };
+
+ ducati_cm: ducati_cm@900 {
+ compatible = "ti,omap4-cm";
+ reg = <0x900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x900 0x100>;
+
+ ducati_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_dma_cm: l3_dma_cm@a00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xa00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa00 0x100>;
+
+ l3_dma_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_emif_cm: l3_emif_cm@b00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xb00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xb00 0x100>;
+
+ l3_emif_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x1c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ d2d_cm: d2d_cm@c00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xc00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xc00 0x100>;
+
+ d2d_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_cfg_cm: l4_cfg_cm@d00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xd00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xd00 0x100>;
+
+ l4_cfg_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x14>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_instr_cm: l3_instr_cm@e00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xe00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xe00 0x100>;
+
+ l3_instr_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x24>;
+ #clock-cells = <2>;
+ };
+ };
+
+ ivahd_cm: ivahd_cm@f00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xf00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xf00 0x100>;
+
+ ivahd_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc>;
+ #clock-cells = <2>;
+ };
+ };
+
+ iss_cm: iss_cm@1000 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1000 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x100>;
+
+ iss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_dss_cm: l3_dss_cm@1100 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1100 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1100 0x100>;
+
+ l3_dss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_gfx_cm: l3_gfx_cm@1200 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1200 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1200 0x100>;
+
+ l3_gfx_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3_init_cm: l3_init_cm@1300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1300 0x100>;
+
+ l3_init_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4_per_cm: l4_per_cm@1400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1400 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1400 0x200>;
+
+ l4_per_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x144>;
+ #clock-cells = <2>;
+ };
+ };
+
+};
+
+&prm {
+ l4_wkup_cm: l4_wkup_cm@1800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1800 0x100>;
+
+ l4_wkup_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x5c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ emu_sys_cm: emu_sys_cm@1a00 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1a00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1a00 0x100>;
+
+ emu_sys_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 51a7fb3d7b9a..35d4298da83d 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>
+#include <dt-bindings/clock/omap5.h>
/ {
#address-cells = <2>;
@@ -201,8 +202,12 @@
};
cm_core_aon: cm_core_aon@4000 {
- compatible = "ti,omap5-cm-core-aon";
+ compatible = "ti,omap5-cm-core-aon",
+ "simple-bus";
reg = <0x4000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x4000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
@@ -214,8 +219,11 @@
};
cm_core: cm_core@8000 {
- compatible = "ti,omap5-cm-core";
+ compatible = "ti,omap5-cm-core", "simple-bus";
reg = <0x8000 0x3000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x8000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
@@ -240,9 +248,12 @@
};
prm: prm@6000 {
- compatible = "ti,omap5-prm";
+ compatible = "ti,omap5-prm", "simple-bus";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x6000 0x3000>;
prm_clocks: clocks {
#address-cells = <1>;
@@ -734,6 +745,8 @@
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "timer1";
ti,timer-alwon;
+ clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
+ clock-names = "fck";
};
timer2: timer@48032000 {
@@ -893,7 +906,8 @@
compatible = "ti,omap-usb2";
reg = <0x4a084000 0x7c>;
syscon-phy-power = <&scm_conf 0x300>;
- clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
+ clocks = <&usb_phy_cm_clk32k>,
+ <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
clock-names = "wkupclk", "refclk";
#phy-cells = <0>;
};
@@ -907,7 +921,7 @@
syscon-phy-power = <&scm_conf 0x370>;
clocks = <&usb_phy_cm_clk32k>,
<&sys_clkin>,
- <&usb_otg_ss_refclk960m>;
+ <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
clock-names = "wkupclk",
"sysclk",
"refclk";
@@ -976,7 +990,8 @@
<0x4A096800 0x40>; /* pll_ctrl */
reg-names = "phy_rx", "phy_tx", "pll_ctrl";
syscon-phy-power = <&scm_conf 0x374>;
- clocks = <&sys_clkin>, <&sata_ref_clk>;
+ clocks = <&sys_clkin>,
+ <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
clock-names = "sysclk", "refclk";
#phy-cells = <0>;
};
@@ -988,7 +1003,7 @@
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
phys = <&sata_phy>;
phy-names = "sata-phy";
- clocks = <&sata_ref_clk>;
+ clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
ti,hwmods = "sata";
ports-implemented = <0x1>;
};
@@ -998,7 +1013,7 @@
reg = <0x58000000 0x80>;
status = "disabled";
ti,hwmods = "dss_core";
- clocks = <&dss_dss_clk>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
@@ -1009,7 +1024,7 @@
reg = <0x58001000 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "dss_dispc";
- clocks = <&dss_dss_clk>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
};
@@ -1018,7 +1033,7 @@
reg = <0x58002000 0x100>;
status = "disabled";
ti,hwmods = "dss_rfbi";
- clocks = <&dss_dss_clk>, <&l3_iclk_div>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
clock-names = "fck", "ick";
};
@@ -1031,7 +1046,8 @@
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_dsi1";
- clocks = <&dss_dss_clk>, <&dss_sys_clk>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
@@ -1044,7 +1060,8 @@
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_dsi2";
- clocks = <&dss_dss_clk>, <&dss_sys_clk>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
@@ -1058,7 +1075,8 @@
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
ti,hwmods = "dss_hdmi";
- clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
+ clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
+ <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
dmas = <&sdma 76>;
dma-names = "audio_tx";
@@ -1132,7 +1150,7 @@
coefficients = <65 (-1791)>;
};
-/include/ "omap54xx-clocks.dtsi"
+#include "omap54xx-clocks.dtsi"
&gpu_thermal {
coefficients = <117 (-2992)>;
diff --git a/arch/arm/boot/dts/omap54xx-clocks.dtsi b/arch/arm/boot/dts/omap54xx-clocks.dtsi
index 529193442620..9619a746d657 100644
--- a/arch/arm/boot/dts/omap54xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap54xx-clocks.dtsi
@@ -432,22 +432,6 @@
reg = <0x0528>;
};
- dmic_sync_mux_ck: dmic_sync_mux_ck@538 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
- ti,bit-shift = <26>;
- reg = <0x0538>;
- };
-
- dmic_gfclk: dmic_gfclk@538 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0538>;
- };
-
mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -464,86 +448,6 @@
reg = <0x0540>;
};
- mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck@548 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
- ti,bit-shift = <26>;
- reg = <0x0548>;
- };
-
- mcbsp1_gfclk: mcbsp1_gfclk@548 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0548>;
- };
-
- mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck@550 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
- ti,bit-shift = <26>;
- reg = <0x0550>;
- };
-
- mcbsp2_gfclk: mcbsp2_gfclk@550 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0550>;
- };
-
- mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck@558 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
- ti,bit-shift = <26>;
- reg = <0x0558>;
- };
-
- mcbsp3_gfclk: mcbsp3_gfclk@558 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0558>;
- };
-
- timer5_gfclk_mux: timer5_gfclk_mux@568 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0568>;
- };
-
- timer6_gfclk_mux: timer6_gfclk_mux@570 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0570>;
- };
-
- timer7_gfclk_mux: timer7_gfclk_mux@578 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0578>;
- };
-
- timer8_gfclk_mux: timer8_gfclk_mux@580 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x0580>;
- };
-
dummy_ck: dummy_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -603,23 +507,8 @@
clock-mult = <1>;
clock-div = <1>;
};
-
- gpio1_dbclk: gpio1_dbclk@1938 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1938>;
- };
-
- timer1_gfclk_mux: timer1_gfclk_mux@1940 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1940>;
- };
};
+
&cm_core_clocks {
dpll_per_byp_mux: dpll_per_byp_mux@14c {
@@ -825,95 +714,6 @@
ti,dividers = <1>, <8>;
};
- dss_32khz_clk: dss_32khz_clk@1420 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <11>;
- reg = <0x1420>;
- };
-
- dss_48mhz_clk: dss_48mhz_clk@1420 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_48m_fclk>;
- ti,bit-shift = <9>;
- reg = <0x1420>;
- };
-
- dss_dss_clk: dss_dss_clk@1420 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_per_h12x2_ck>;
- ti,bit-shift = <8>;
- reg = <0x1420>;
- ti,set-rate-parent;
- };
-
- dss_sys_clk: dss_sys_clk@1420 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dss_syc_gfclk_div>;
- ti,bit-shift = <10>;
- reg = <0x1420>;
- };
-
- gpio2_dbclk: gpio2_dbclk@1060 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1060>;
- };
-
- gpio3_dbclk: gpio3_dbclk@1068 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1068>;
- };
-
- gpio4_dbclk: gpio4_dbclk@1070 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1070>;
- };
-
- gpio5_dbclk: gpio5_dbclk@1078 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1078>;
- };
-
- gpio6_dbclk: gpio6_dbclk@1080 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1080>;
- };
-
- gpio7_dbclk: gpio7_dbclk@1110 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1110>;
- };
-
- gpio8_dbclk: gpio8_dbclk@1118 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1118>;
- };
-
iss_ctrlclk: iss_ctrlclk@1320 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -938,118 +738,6 @@
reg = <0x0f20>;
};
- mmc1_32khz_clk: mmc1_32khz_clk@1628 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x1628>;
- };
-
- sata_ref_clk: sata_ref_clk@1688 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_clkin>;
- ti,bit-shift = <8>;
- reg = <0x1688>;
- };
-
- usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_usb_m2_ck>;
- ti,bit-shift = <13>;
- reg = <0x1658>;
- };
-
- usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_usb_m2_ck>;
- ti,bit-shift = <14>;
- reg = <0x1658>;
- };
-
- usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_usb_m2_ck>;
- ti,bit-shift = <7>;
- reg = <0x1658>;
- };
-
- usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_60m_fclk>;
- ti,bit-shift = <11>;
- reg = <0x1658>;
- };
-
- usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_60m_fclk>;
- ti,bit-shift = <12>;
- reg = <0x1658>;
- };
-
- usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_60m_fclk>;
- ti,bit-shift = <6>;
- reg = <0x1658>;
- };
-
- utmi_p1_gfclk: utmi_p1_gfclk@1658 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
- ti,bit-shift = <24>;
- reg = <0x1658>;
- };
-
- usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&utmi_p1_gfclk>;
- ti,bit-shift = <8>;
- reg = <0x1658>;
- };
-
- utmi_p2_gfclk: utmi_p2_gfclk@1658 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
- ti,bit-shift = <25>;
- reg = <0x1658>;
- };
-
- usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&utmi_p2_gfclk>;
- ti,bit-shift = <9>;
- reg = <0x1658>;
- };
-
- usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk@1658 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_60m_fclk>;
- ti,bit-shift = <10>;
- reg = <0x1658>;
- };
-
- usb_otg_ss_refclk960m: usb_otg_ss_refclk960m@16f0 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_usb_clkdcoldo>;
- ti,bit-shift = <8>;
- reg = <0x16f0>;
- };
-
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -1058,30 +746,6 @@
reg = <0x0640>;
};
- usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk@1668 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_60m_fclk>;
- ti,bit-shift = <8>;
- reg = <0x1668>;
- };
-
- usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk@1668 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_60m_fclk>;
- ti,bit-shift = <9>;
- reg = <0x1668>;
- };
-
- usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk@1668 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&l3init_60m_fclk>;
- ti,bit-shift = <10>;
- reg = <0x1668>;
- };
-
fdif_fclk: fdif_fclk@1328 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
@@ -1115,88 +779,6 @@
ti,max-div = <2>;
reg = <0x1638>;
};
-
- mmc1_fclk_mux: mmc1_fclk_mux@1628 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1628>;
- };
-
- mmc1_fclk: mmc1_fclk@1628 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&mmc1_fclk_mux>;
- ti,bit-shift = <25>;
- ti,max-div = <2>;
- reg = <0x1628>;
- };
-
- mmc2_fclk_mux: mmc2_fclk_mux@1630 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1630>;
- };
-
- mmc2_fclk: mmc2_fclk@1630 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&mmc2_fclk_mux>;
- ti,bit-shift = <25>;
- ti,max-div = <2>;
- reg = <0x1630>;
- };
-
- timer10_gfclk_mux: timer10_gfclk_mux@1028 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1028>;
- };
-
- timer11_gfclk_mux: timer11_gfclk_mux@1030 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1030>;
- };
-
- timer2_gfclk_mux: timer2_gfclk_mux@1038 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1038>;
- };
-
- timer3_gfclk_mux: timer3_gfclk_mux@1040 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1040>;
- };
-
- timer4_gfclk_mux: timer4_gfclk_mux@1048 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1048>;
- };
-
- timer9_gfclk_mux: timer9_gfclk_mux@1050 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- ti,bit-shift = <24>;
- reg = <0x1050>;
- };
};
&cm_core_clockdomains {
@@ -1394,3 +976,206 @@
reg = <0x021c>;
};
};
+
+&cm_core_aon {
+ mpu_cm: mpu_cm@300 {
+ compatible = "ti,omap4-cm";
+ reg = <0x300 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x300 0x100>;
+
+ mpu_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ dsp_cm: dsp_cm@400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x400 0x100>;
+
+ dsp_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ abe_cm: abe_cm@500 {
+ compatible = "ti,omap4-cm";
+ reg = <0x500 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x500 0x100>;
+
+ abe_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x64>;
+ #clock-cells = <2>;
+ };
+ };
+
+};
+
+&cm_core {
+ l3main1_cm: l3main1_cm@700 {
+ compatible = "ti,omap4-cm";
+ reg = <0x700 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x700 0x100>;
+
+ l3main1_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3main2_cm: l3main2_cm@800 {
+ compatible = "ti,omap4-cm";
+ reg = <0x800 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x800 0x100>;
+
+ l3main2_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ ipu_cm: ipu_cm@900 {
+ compatible = "ti,omap4-cm";
+ reg = <0x900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x900 0x100>;
+
+ ipu_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ dma_cm: dma_cm@a00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xa00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xa00 0x100>;
+
+ dma_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ emif_cm: emif_cm@b00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xb00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xb00 0x100>;
+
+ emif_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x1c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4cfg_cm: l4cfg_cm@d00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xd00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xd00 0x100>;
+
+ l4cfg_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x14>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3instr_cm: l3instr_cm@e00 {
+ compatible = "ti,omap4-cm";
+ reg = <0xe00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xe00 0x100>;
+
+ l3instr_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xc>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l4per_cm: l4per_cm@1000 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1000 0x200>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1000 0x200>;
+
+ l4per_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x15c>;
+ #clock-cells = <2>;
+ };
+ };
+
+ dss_cm: dss_cm@1400 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1400 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1400 0x100>;
+
+ dss_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x4>;
+ #clock-cells = <2>;
+ };
+ };
+
+ l3init_cm: l3init_cm@1600 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1600 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1600 0x100>;
+
+ l3init_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0xd4>;
+ #clock-cells = <2>;
+ };
+ };
+};
+
+&prm {
+ wkupaon_cm: wkupaon_cm@1900 {
+ compatible = "ti,omap4-cm";
+ reg = <0x1900 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x1900 0x100>;
+
+ wkupaon_clkctrl: clk@20 {
+ compatible = "ti,clkctrl";
+ reg = <0x20 0x5c>;
+ #clock-cells = <2>;
+ };
+ };
+};
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-13 04:39:33 +0000